1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8795 switch driver 4 * 5 * Copyright (C) 2017 Microchip Technology Inc. 6 * Tristram Ha <Tristram.Ha@microchip.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/gpio.h> 13 #include <linux/if_vlan.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_data/microchip-ksz.h> 17 #include <linux/phy.h> 18 #include <linux/etherdevice.h> 19 #include <linux/if_bridge.h> 20 #include <linux/micrel_phy.h> 21 #include <net/dsa.h> 22 #include <net/switchdev.h> 23 #include <linux/phylink.h> 24 25 #include "ksz_common.h" 26 #include "ksz8795_reg.h" 27 #include "ksz8.h" 28 29 static const u8 ksz8795_regs[] = { 30 [REG_IND_CTRL_0] = 0x6E, 31 [REG_IND_DATA_8] = 0x70, 32 [REG_IND_DATA_CHECK] = 0x72, 33 [REG_IND_DATA_HI] = 0x71, 34 [REG_IND_DATA_LO] = 0x75, 35 [REG_IND_MIB_CHECK] = 0x74, 36 [REG_IND_BYTE] = 0xA0, 37 [P_FORCE_CTRL] = 0x0C, 38 [P_LINK_STATUS] = 0x0E, 39 [P_LOCAL_CTRL] = 0x07, 40 [P_NEG_RESTART_CTRL] = 0x0D, 41 [P_REMOTE_STATUS] = 0x08, 42 [P_SPEED_STATUS] = 0x09, 43 [S_TAIL_TAG_CTRL] = 0x0C, 44 }; 45 46 static const u32 ksz8795_masks[] = { 47 [PORT_802_1P_REMAPPING] = BIT(7), 48 [SW_TAIL_TAG_ENABLE] = BIT(1), 49 [MIB_COUNTER_OVERFLOW] = BIT(6), 50 [MIB_COUNTER_VALID] = BIT(5), 51 [VLAN_TABLE_FID] = GENMASK(6, 0), 52 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 53 [VLAN_TABLE_VALID] = BIT(12), 54 [STATIC_MAC_TABLE_VALID] = BIT(21), 55 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 56 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 57 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 58 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 59 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 60 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 61 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 62 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 63 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 64 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 65 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 66 }; 67 68 static const u8 ksz8795_shifts[] = { 69 [VLAN_TABLE_MEMBERSHIP_S] = 7, 70 [VLAN_TABLE] = 16, 71 [STATIC_MAC_FWD_PORTS] = 16, 72 [STATIC_MAC_FID] = 24, 73 [DYNAMIC_MAC_ENTRIES_H] = 3, 74 [DYNAMIC_MAC_ENTRIES] = 29, 75 [DYNAMIC_MAC_FID] = 16, 76 [DYNAMIC_MAC_TIMESTAMP] = 27, 77 [DYNAMIC_MAC_SRC_PORT] = 24, 78 }; 79 80 static const u8 ksz8863_regs[] = { 81 [REG_IND_CTRL_0] = 0x79, 82 [REG_IND_DATA_8] = 0x7B, 83 [REG_IND_DATA_CHECK] = 0x7B, 84 [REG_IND_DATA_HI] = 0x7C, 85 [REG_IND_DATA_LO] = 0x80, 86 [REG_IND_MIB_CHECK] = 0x80, 87 [P_FORCE_CTRL] = 0x0C, 88 [P_LINK_STATUS] = 0x0E, 89 [P_LOCAL_CTRL] = 0x0C, 90 [P_NEG_RESTART_CTRL] = 0x0D, 91 [P_REMOTE_STATUS] = 0x0E, 92 [P_SPEED_STATUS] = 0x0F, 93 [S_TAIL_TAG_CTRL] = 0x03, 94 }; 95 96 static const u32 ksz8863_masks[] = { 97 [PORT_802_1P_REMAPPING] = BIT(3), 98 [SW_TAIL_TAG_ENABLE] = BIT(6), 99 [MIB_COUNTER_OVERFLOW] = BIT(7), 100 [MIB_COUNTER_VALID] = BIT(6), 101 [VLAN_TABLE_FID] = GENMASK(15, 12), 102 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 103 [VLAN_TABLE_VALID] = BIT(19), 104 [STATIC_MAC_TABLE_VALID] = BIT(19), 105 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 106 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 107 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 108 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 109 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 110 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 111 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 112 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 113 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 114 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 115 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 116 }; 117 118 static u8 ksz8863_shifts[] = { 119 [VLAN_TABLE_MEMBERSHIP_S] = 16, 120 [STATIC_MAC_FWD_PORTS] = 16, 121 [STATIC_MAC_FID] = 22, 122 [DYNAMIC_MAC_ENTRIES_H] = 3, 123 [DYNAMIC_MAC_ENTRIES] = 24, 124 [DYNAMIC_MAC_FID] = 16, 125 [DYNAMIC_MAC_TIMESTAMP] = 24, 126 [DYNAMIC_MAC_SRC_PORT] = 20, 127 }; 128 129 static bool ksz_is_ksz88x3(struct ksz_device *dev) 130 { 131 return dev->chip_id == 0x8830; 132 } 133 134 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 135 { 136 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 137 } 138 139 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 140 bool set) 141 { 142 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 143 bits, set ? bits : 0); 144 } 145 146 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data) 147 { 148 struct ksz8 *ksz8 = dev->priv; 149 const u8 *regs = ksz8->regs; 150 u16 ctrl_addr; 151 int ret = 0; 152 153 mutex_lock(&dev->alu_mutex); 154 155 ctrl_addr = IND_ACC_TABLE(table) | addr; 156 ret = ksz_write8(dev, regs[REG_IND_BYTE], data); 157 if (!ret) 158 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 159 160 mutex_unlock(&dev->alu_mutex); 161 162 return ret; 163 } 164 165 int ksz8_reset_switch(struct ksz_device *dev) 166 { 167 if (ksz_is_ksz88x3(dev)) { 168 /* reset switch */ 169 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 170 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 171 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 172 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 173 } else { 174 /* reset switch */ 175 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 176 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 177 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 178 } 179 180 return 0; 181 } 182 183 static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue) 184 { 185 u8 hi, lo; 186 187 /* Number of queues can only be 1, 2, or 4. */ 188 switch (queue) { 189 case 4: 190 case 3: 191 queue = PORT_QUEUE_SPLIT_4; 192 break; 193 case 2: 194 queue = PORT_QUEUE_SPLIT_2; 195 break; 196 default: 197 queue = PORT_QUEUE_SPLIT_1; 198 } 199 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo); 200 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi); 201 lo &= ~PORT_QUEUE_SPLIT_L; 202 if (queue & PORT_QUEUE_SPLIT_2) 203 lo |= PORT_QUEUE_SPLIT_L; 204 hi &= ~PORT_QUEUE_SPLIT_H; 205 if (queue & PORT_QUEUE_SPLIT_4) 206 hi |= PORT_QUEUE_SPLIT_H; 207 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo); 208 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi); 209 210 /* Default is port based for egress rate limit. */ 211 if (queue != PORT_QUEUE_SPLIT_1) 212 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED, 213 true); 214 } 215 216 void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 217 { 218 struct ksz8 *ksz8 = dev->priv; 219 const u32 *masks; 220 const u8 *regs; 221 u16 ctrl_addr; 222 u32 data; 223 u8 check; 224 int loop; 225 226 masks = ksz8->masks; 227 regs = ksz8->regs; 228 229 ctrl_addr = addr + dev->info->reg_mib_cnt * port; 230 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 231 232 mutex_lock(&dev->alu_mutex); 233 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 234 235 /* It is almost guaranteed to always read the valid bit because of 236 * slow SPI speed. 237 */ 238 for (loop = 2; loop > 0; loop--) { 239 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 240 241 if (check & masks[MIB_COUNTER_VALID]) { 242 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 243 if (check & masks[MIB_COUNTER_OVERFLOW]) 244 *cnt += MIB_COUNTER_VALUE + 1; 245 *cnt += data & MIB_COUNTER_VALUE; 246 break; 247 } 248 } 249 mutex_unlock(&dev->alu_mutex); 250 } 251 252 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 253 u64 *dropped, u64 *cnt) 254 { 255 struct ksz8 *ksz8 = dev->priv; 256 const u32 *masks; 257 const u8 *regs; 258 u16 ctrl_addr; 259 u32 data; 260 u8 check; 261 int loop; 262 263 masks = ksz8->masks; 264 regs = ksz8->regs; 265 266 addr -= dev->info->reg_mib_cnt; 267 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 268 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 269 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 270 271 mutex_lock(&dev->alu_mutex); 272 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 273 274 /* It is almost guaranteed to always read the valid bit because of 275 * slow SPI speed. 276 */ 277 for (loop = 2; loop > 0; loop--) { 278 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 279 280 if (check & masks[MIB_COUNTER_VALID]) { 281 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 282 if (addr < 2) { 283 u64 total; 284 285 total = check & MIB_TOTAL_BYTES_H; 286 total <<= 32; 287 *cnt += total; 288 *cnt += data; 289 if (check & masks[MIB_COUNTER_OVERFLOW]) { 290 total = MIB_TOTAL_BYTES_H + 1; 291 total <<= 32; 292 *cnt += total; 293 } 294 } else { 295 if (check & masks[MIB_COUNTER_OVERFLOW]) 296 *cnt += MIB_PACKET_DROPPED + 1; 297 *cnt += data & MIB_PACKET_DROPPED; 298 } 299 break; 300 } 301 } 302 mutex_unlock(&dev->alu_mutex); 303 } 304 305 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 306 u64 *dropped, u64 *cnt) 307 { 308 struct ksz8 *ksz8 = dev->priv; 309 const u8 *regs = ksz8->regs; 310 u32 *last = (u32 *)dropped; 311 u16 ctrl_addr; 312 u32 data; 313 u32 cur; 314 315 addr -= dev->info->reg_mib_cnt; 316 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 317 KSZ8863_MIB_PACKET_DROPPED_RX_0; 318 ctrl_addr += port; 319 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 320 321 mutex_lock(&dev->alu_mutex); 322 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 323 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 324 mutex_unlock(&dev->alu_mutex); 325 326 data &= MIB_PACKET_DROPPED; 327 cur = last[addr]; 328 if (data != cur) { 329 last[addr] = data; 330 if (data < cur) 331 data += MIB_PACKET_DROPPED + 1; 332 data -= cur; 333 *cnt += data; 334 } 335 } 336 337 void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 338 u64 *dropped, u64 *cnt) 339 { 340 if (ksz_is_ksz88x3(dev)) 341 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 342 else 343 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 344 } 345 346 void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 347 { 348 if (ksz_is_ksz88x3(dev)) 349 return; 350 351 /* enable the port for flush/freeze function */ 352 if (freeze) 353 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 354 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 355 356 /* disable the port after freeze is done */ 357 if (!freeze) 358 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 359 } 360 361 void ksz8_port_init_cnt(struct ksz_device *dev, int port) 362 { 363 struct ksz_port_mib *mib = &dev->ports[port].mib; 364 u64 *dropped; 365 366 if (!ksz_is_ksz88x3(dev)) { 367 /* flush all enabled port MIB counters */ 368 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 369 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 370 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 371 } 372 373 mib->cnt_ptr = 0; 374 375 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 376 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 377 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 378 &mib->counters[mib->cnt_ptr]); 379 ++mib->cnt_ptr; 380 } 381 382 /* last one in storage */ 383 dropped = &mib->counters[dev->info->mib_cnt]; 384 385 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 386 while (mib->cnt_ptr < dev->info->mib_cnt) { 387 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 388 dropped, &mib->counters[mib->cnt_ptr]); 389 ++mib->cnt_ptr; 390 } 391 } 392 393 static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 394 { 395 struct ksz8 *ksz8 = dev->priv; 396 const u8 *regs = ksz8->regs; 397 u16 ctrl_addr; 398 399 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 400 401 mutex_lock(&dev->alu_mutex); 402 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 403 ksz_read64(dev, regs[REG_IND_DATA_HI], data); 404 mutex_unlock(&dev->alu_mutex); 405 } 406 407 static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 408 { 409 struct ksz8 *ksz8 = dev->priv; 410 const u8 *regs = ksz8->regs; 411 u16 ctrl_addr; 412 413 ctrl_addr = IND_ACC_TABLE(table) | addr; 414 415 mutex_lock(&dev->alu_mutex); 416 ksz_write64(dev, regs[REG_IND_DATA_HI], data); 417 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 418 mutex_unlock(&dev->alu_mutex); 419 } 420 421 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 422 { 423 struct ksz8 *ksz8 = dev->priv; 424 int timeout = 100; 425 const u32 *masks; 426 const u8 *regs; 427 428 masks = ksz8->masks; 429 regs = ksz8->regs; 430 431 do { 432 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 433 timeout--; 434 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 435 436 /* Entry is not ready for accessing. */ 437 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) { 438 return -EAGAIN; 439 /* Entry is ready for accessing. */ 440 } else { 441 ksz_read8(dev, regs[REG_IND_DATA_8], data); 442 443 /* There is no valid entry in the table. */ 444 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) 445 return -ENXIO; 446 } 447 return 0; 448 } 449 450 int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr, 451 u8 *fid, u8 *src_port, u8 *timestamp, u16 *entries) 452 { 453 struct ksz8 *ksz8 = dev->priv; 454 u32 data_hi, data_lo; 455 const u8 *shifts; 456 const u32 *masks; 457 const u8 *regs; 458 u16 ctrl_addr; 459 u8 data; 460 int rc; 461 462 shifts = ksz8->shifts; 463 masks = ksz8->masks; 464 regs = ksz8->regs; 465 466 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 467 468 mutex_lock(&dev->alu_mutex); 469 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 470 471 rc = ksz8_valid_dyn_entry(dev, &data); 472 if (rc == -EAGAIN) { 473 if (addr == 0) 474 *entries = 0; 475 } else if (rc == -ENXIO) { 476 *entries = 0; 477 /* At least one valid entry in the table. */ 478 } else { 479 u64 buf = 0; 480 int cnt; 481 482 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 483 data_hi = (u32)(buf >> 32); 484 data_lo = (u32)buf; 485 486 /* Check out how many valid entry in the table. */ 487 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 488 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 489 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 490 shifts[DYNAMIC_MAC_ENTRIES]; 491 *entries = cnt + 1; 492 493 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 494 shifts[DYNAMIC_MAC_FID]; 495 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 496 shifts[DYNAMIC_MAC_SRC_PORT]; 497 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >> 498 shifts[DYNAMIC_MAC_TIMESTAMP]; 499 500 mac_addr[5] = (u8)data_lo; 501 mac_addr[4] = (u8)(data_lo >> 8); 502 mac_addr[3] = (u8)(data_lo >> 16); 503 mac_addr[2] = (u8)(data_lo >> 24); 504 505 mac_addr[1] = (u8)data_hi; 506 mac_addr[0] = (u8)(data_hi >> 8); 507 rc = 0; 508 } 509 mutex_unlock(&dev->alu_mutex); 510 511 return rc; 512 } 513 514 int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 515 struct alu_struct *alu) 516 { 517 struct ksz8 *ksz8 = dev->priv; 518 u32 data_hi, data_lo; 519 const u8 *shifts; 520 const u32 *masks; 521 u64 data; 522 523 shifts = ksz8->shifts; 524 masks = ksz8->masks; 525 526 ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 527 data_hi = data >> 32; 528 data_lo = (u32)data; 529 if (data_hi & (masks[STATIC_MAC_TABLE_VALID] | 530 masks[STATIC_MAC_TABLE_OVERRIDE])) { 531 alu->mac[5] = (u8)data_lo; 532 alu->mac[4] = (u8)(data_lo >> 8); 533 alu->mac[3] = (u8)(data_lo >> 16); 534 alu->mac[2] = (u8)(data_lo >> 24); 535 alu->mac[1] = (u8)data_hi; 536 alu->mac[0] = (u8)(data_hi >> 8); 537 alu->port_forward = 538 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 539 shifts[STATIC_MAC_FWD_PORTS]; 540 alu->is_override = 541 (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 542 data_hi >>= 1; 543 alu->is_static = true; 544 alu->is_use_fid = 545 (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 546 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 547 shifts[STATIC_MAC_FID]; 548 return 0; 549 } 550 return -ENXIO; 551 } 552 553 void ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 554 struct alu_struct *alu) 555 { 556 struct ksz8 *ksz8 = dev->priv; 557 u32 data_hi, data_lo; 558 const u8 *shifts; 559 const u32 *masks; 560 u64 data; 561 562 shifts = ksz8->shifts; 563 masks = ksz8->masks; 564 565 data_lo = ((u32)alu->mac[2] << 24) | 566 ((u32)alu->mac[3] << 16) | 567 ((u32)alu->mac[4] << 8) | alu->mac[5]; 568 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 569 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 570 571 if (alu->is_override) 572 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 573 if (alu->is_use_fid) { 574 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 575 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 576 } 577 if (alu->is_static) 578 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 579 else 580 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 581 582 data = (u64)data_hi << 32 | data_lo; 583 ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 584 } 585 586 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 587 u8 *member, u8 *valid) 588 { 589 struct ksz8 *ksz8 = dev->priv; 590 const u8 *shifts; 591 const u32 *masks; 592 593 shifts = ksz8->shifts; 594 masks = ksz8->masks; 595 596 *fid = vlan & masks[VLAN_TABLE_FID]; 597 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 598 shifts[VLAN_TABLE_MEMBERSHIP_S]; 599 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 600 } 601 602 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 603 u16 *vlan) 604 { 605 struct ksz8 *ksz8 = dev->priv; 606 const u8 *shifts; 607 const u32 *masks; 608 609 shifts = ksz8->shifts; 610 masks = ksz8->masks; 611 612 *vlan = fid; 613 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 614 if (valid) 615 *vlan |= masks[VLAN_TABLE_VALID]; 616 } 617 618 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 619 { 620 struct ksz8 *ksz8 = dev->priv; 621 const u8 *shifts; 622 u64 data; 623 int i; 624 625 shifts = ksz8->shifts; 626 627 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 628 addr *= 4; 629 for (i = 0; i < 4; i++) { 630 dev->vlan_cache[addr + i].table[0] = (u16)data; 631 data >>= shifts[VLAN_TABLE]; 632 } 633 } 634 635 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 636 { 637 int index; 638 u16 *data; 639 u16 addr; 640 u64 buf; 641 642 data = (u16 *)&buf; 643 addr = vid / 4; 644 index = vid & 3; 645 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 646 *vlan = data[index]; 647 } 648 649 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 650 { 651 int index; 652 u16 *data; 653 u16 addr; 654 u64 buf; 655 656 data = (u16 *)&buf; 657 addr = vid / 4; 658 index = vid & 3; 659 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 660 data[index] = vlan; 661 dev->vlan_cache[vid].table[0] = vlan; 662 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 663 } 664 665 void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 666 { 667 struct ksz8 *ksz8 = dev->priv; 668 u8 restart, speed, ctrl, link; 669 const u8 *regs = ksz8->regs; 670 int processed = true; 671 u8 val1, val2; 672 u16 data = 0; 673 u8 p = phy; 674 675 switch (reg) { 676 case MII_BMCR: 677 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 678 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 679 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 680 if (restart & PORT_PHY_LOOPBACK) 681 data |= BMCR_LOOPBACK; 682 if (ctrl & PORT_FORCE_100_MBIT) 683 data |= BMCR_SPEED100; 684 if (ksz_is_ksz88x3(dev)) { 685 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 686 data |= BMCR_ANENABLE; 687 } else { 688 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 689 data |= BMCR_ANENABLE; 690 } 691 if (restart & PORT_POWER_DOWN) 692 data |= BMCR_PDOWN; 693 if (restart & PORT_AUTO_NEG_RESTART) 694 data |= BMCR_ANRESTART; 695 if (ctrl & PORT_FORCE_FULL_DUPLEX) 696 data |= BMCR_FULLDPLX; 697 if (speed & PORT_HP_MDIX) 698 data |= KSZ886X_BMCR_HP_MDIX; 699 if (restart & PORT_FORCE_MDIX) 700 data |= KSZ886X_BMCR_FORCE_MDI; 701 if (restart & PORT_AUTO_MDIX_DISABLE) 702 data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX; 703 if (restart & PORT_TX_DISABLE) 704 data |= KSZ886X_BMCR_DISABLE_TRANSMIT; 705 if (restart & PORT_LED_OFF) 706 data |= KSZ886X_BMCR_DISABLE_LED; 707 break; 708 case MII_BMSR: 709 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 710 data = BMSR_100FULL | 711 BMSR_100HALF | 712 BMSR_10FULL | 713 BMSR_10HALF | 714 BMSR_ANEGCAPABLE; 715 if (link & PORT_AUTO_NEG_COMPLETE) 716 data |= BMSR_ANEGCOMPLETE; 717 if (link & PORT_STAT_LINK_GOOD) 718 data |= BMSR_LSTATUS; 719 break; 720 case MII_PHYSID1: 721 data = KSZ8795_ID_HI; 722 break; 723 case MII_PHYSID2: 724 if (ksz_is_ksz88x3(dev)) 725 data = KSZ8863_ID_LO; 726 else 727 data = KSZ8795_ID_LO; 728 break; 729 case MII_ADVERTISE: 730 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 731 data = ADVERTISE_CSMA; 732 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 733 data |= ADVERTISE_PAUSE_CAP; 734 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 735 data |= ADVERTISE_100FULL; 736 if (ctrl & PORT_AUTO_NEG_100BTX) 737 data |= ADVERTISE_100HALF; 738 if (ctrl & PORT_AUTO_NEG_10BT_FD) 739 data |= ADVERTISE_10FULL; 740 if (ctrl & PORT_AUTO_NEG_10BT) 741 data |= ADVERTISE_10HALF; 742 break; 743 case MII_LPA: 744 ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 745 data = LPA_SLCT; 746 if (link & PORT_REMOTE_SYM_PAUSE) 747 data |= LPA_PAUSE_CAP; 748 if (link & PORT_REMOTE_100BTX_FD) 749 data |= LPA_100FULL; 750 if (link & PORT_REMOTE_100BTX) 751 data |= LPA_100HALF; 752 if (link & PORT_REMOTE_10BT_FD) 753 data |= LPA_10FULL; 754 if (link & PORT_REMOTE_10BT) 755 data |= LPA_10HALF; 756 if (data & ~LPA_SLCT) 757 data |= LPA_LPACK; 758 break; 759 case PHY_REG_LINK_MD: 760 ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1); 761 ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2); 762 if (val1 & PORT_START_CABLE_DIAG) 763 data |= PHY_START_CABLE_DIAG; 764 765 if (val1 & PORT_CABLE_10M_SHORT) 766 data |= PHY_CABLE_10M_SHORT; 767 768 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M, 769 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1)); 770 771 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M, 772 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) | 773 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2)); 774 break; 775 case PHY_REG_PHY_CTRL: 776 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 777 if (link & PORT_MDIX_STATUS) 778 data |= KSZ886X_CTRL_MDIX_STAT; 779 break; 780 default: 781 processed = false; 782 break; 783 } 784 if (processed) 785 *val = data; 786 } 787 788 void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 789 { 790 struct ksz8 *ksz8 = dev->priv; 791 u8 restart, speed, ctrl, data; 792 const u8 *regs = ksz8->regs; 793 u8 p = phy; 794 795 switch (reg) { 796 case MII_BMCR: 797 798 /* Do not support PHY reset function. */ 799 if (val & BMCR_RESET) 800 break; 801 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 802 data = speed; 803 if (val & KSZ886X_BMCR_HP_MDIX) 804 data |= PORT_HP_MDIX; 805 else 806 data &= ~PORT_HP_MDIX; 807 if (data != speed) 808 ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data); 809 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 810 data = ctrl; 811 if (ksz_is_ksz88x3(dev)) { 812 if ((val & BMCR_ANENABLE)) 813 data |= PORT_AUTO_NEG_ENABLE; 814 else 815 data &= ~PORT_AUTO_NEG_ENABLE; 816 } else { 817 if (!(val & BMCR_ANENABLE)) 818 data |= PORT_AUTO_NEG_DISABLE; 819 else 820 data &= ~PORT_AUTO_NEG_DISABLE; 821 822 /* Fiber port does not support auto-negotiation. */ 823 if (dev->ports[p].fiber) 824 data |= PORT_AUTO_NEG_DISABLE; 825 } 826 827 if (val & BMCR_SPEED100) 828 data |= PORT_FORCE_100_MBIT; 829 else 830 data &= ~PORT_FORCE_100_MBIT; 831 if (val & BMCR_FULLDPLX) 832 data |= PORT_FORCE_FULL_DUPLEX; 833 else 834 data &= ~PORT_FORCE_FULL_DUPLEX; 835 if (data != ctrl) 836 ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data); 837 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 838 data = restart; 839 if (val & KSZ886X_BMCR_DISABLE_LED) 840 data |= PORT_LED_OFF; 841 else 842 data &= ~PORT_LED_OFF; 843 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT) 844 data |= PORT_TX_DISABLE; 845 else 846 data &= ~PORT_TX_DISABLE; 847 if (val & BMCR_ANRESTART) 848 data |= PORT_AUTO_NEG_RESTART; 849 else 850 data &= ~(PORT_AUTO_NEG_RESTART); 851 if (val & BMCR_PDOWN) 852 data |= PORT_POWER_DOWN; 853 else 854 data &= ~PORT_POWER_DOWN; 855 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX) 856 data |= PORT_AUTO_MDIX_DISABLE; 857 else 858 data &= ~PORT_AUTO_MDIX_DISABLE; 859 if (val & KSZ886X_BMCR_FORCE_MDI) 860 data |= PORT_FORCE_MDIX; 861 else 862 data &= ~PORT_FORCE_MDIX; 863 if (val & BMCR_LOOPBACK) 864 data |= PORT_PHY_LOOPBACK; 865 else 866 data &= ~PORT_PHY_LOOPBACK; 867 if (data != restart) 868 ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL], data); 869 break; 870 case MII_ADVERTISE: 871 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 872 data = ctrl; 873 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 874 PORT_AUTO_NEG_100BTX_FD | 875 PORT_AUTO_NEG_100BTX | 876 PORT_AUTO_NEG_10BT_FD | 877 PORT_AUTO_NEG_10BT); 878 if (val & ADVERTISE_PAUSE_CAP) 879 data |= PORT_AUTO_NEG_SYM_PAUSE; 880 if (val & ADVERTISE_100FULL) 881 data |= PORT_AUTO_NEG_100BTX_FD; 882 if (val & ADVERTISE_100HALF) 883 data |= PORT_AUTO_NEG_100BTX; 884 if (val & ADVERTISE_10FULL) 885 data |= PORT_AUTO_NEG_10BT_FD; 886 if (val & ADVERTISE_10HALF) 887 data |= PORT_AUTO_NEG_10BT; 888 if (data != ctrl) 889 ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 890 break; 891 case PHY_REG_LINK_MD: 892 if (val & PHY_START_CABLE_DIAG) 893 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true); 894 break; 895 default: 896 break; 897 } 898 } 899 900 void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 901 { 902 u8 data; 903 904 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 905 data &= ~PORT_VLAN_MEMBERSHIP; 906 data |= (member & dev->port_mask); 907 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data); 908 } 909 910 void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port) 911 { 912 u8 learn[DSA_MAX_PORTS]; 913 int first, index, cnt; 914 struct ksz_port *p; 915 916 if ((uint)port < dev->info->port_cnt) { 917 first = port; 918 cnt = port + 1; 919 } else { 920 /* Flush all ports. */ 921 first = 0; 922 cnt = dev->info->port_cnt; 923 } 924 for (index = first; index < cnt; index++) { 925 p = &dev->ports[index]; 926 if (!p->on) 927 continue; 928 ksz_pread8(dev, index, P_STP_CTRL, &learn[index]); 929 if (!(learn[index] & PORT_LEARN_DISABLE)) 930 ksz_pwrite8(dev, index, P_STP_CTRL, 931 learn[index] | PORT_LEARN_DISABLE); 932 } 933 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 934 for (index = first; index < cnt; index++) { 935 p = &dev->ports[index]; 936 if (!p->on) 937 continue; 938 if (!(learn[index] & PORT_LEARN_DISABLE)) 939 ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]); 940 } 941 } 942 943 int ksz8_fdb_dump(struct ksz_device *dev, int port, 944 dsa_fdb_dump_cb_t *cb, void *data) 945 { 946 int ret = 0; 947 u16 i = 0; 948 u16 entries = 0; 949 u8 timestamp = 0; 950 u8 fid; 951 u8 member; 952 struct alu_struct alu; 953 954 do { 955 alu.is_static = false; 956 ret = ksz8_r_dyn_mac_table(dev, i, alu.mac, &fid, &member, 957 ×tamp, &entries); 958 if (!ret && (member & BIT(port))) { 959 ret = cb(alu.mac, alu.fid, alu.is_static, data); 960 if (ret) 961 break; 962 } 963 i++; 964 } while (i < entries); 965 if (i >= entries) 966 ret = 0; 967 968 return ret; 969 } 970 971 int ksz8_mdb_add(struct ksz_device *dev, int port, 972 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 973 { 974 struct alu_struct alu; 975 int index; 976 int empty = 0; 977 978 alu.port_forward = 0; 979 for (index = 0; index < dev->info->num_statics; index++) { 980 if (!ksz8_r_sta_mac_table(dev, index, &alu)) { 981 /* Found one already in static MAC table. */ 982 if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) && 983 alu.fid == mdb->vid) 984 break; 985 /* Remember the first empty entry. */ 986 } else if (!empty) { 987 empty = index + 1; 988 } 989 } 990 991 /* no available entry */ 992 if (index == dev->info->num_statics && !empty) 993 return -ENOSPC; 994 995 /* add entry */ 996 if (index == dev->info->num_statics) { 997 index = empty - 1; 998 memset(&alu, 0, sizeof(alu)); 999 memcpy(alu.mac, mdb->addr, ETH_ALEN); 1000 alu.is_static = true; 1001 } 1002 alu.port_forward |= BIT(port); 1003 if (mdb->vid) { 1004 alu.is_use_fid = true; 1005 1006 /* Need a way to map VID to FID. */ 1007 alu.fid = mdb->vid; 1008 } 1009 ksz8_w_sta_mac_table(dev, index, &alu); 1010 1011 return 0; 1012 } 1013 1014 int ksz8_mdb_del(struct ksz_device *dev, int port, 1015 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 1016 { 1017 struct alu_struct alu; 1018 int index; 1019 1020 for (index = 0; index < dev->info->num_statics; index++) { 1021 if (!ksz8_r_sta_mac_table(dev, index, &alu)) { 1022 /* Found one already in static MAC table. */ 1023 if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) && 1024 alu.fid == mdb->vid) 1025 break; 1026 } 1027 } 1028 1029 /* no available entry */ 1030 if (index == dev->info->num_statics) 1031 goto exit; 1032 1033 /* clear port */ 1034 alu.port_forward &= ~BIT(port); 1035 if (!alu.port_forward) 1036 alu.is_static = false; 1037 ksz8_w_sta_mac_table(dev, index, &alu); 1038 1039 exit: 1040 return 0; 1041 } 1042 1043 int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag, 1044 struct netlink_ext_ack *extack) 1045 { 1046 if (ksz_is_ksz88x3(dev)) 1047 return -ENOTSUPP; 1048 1049 /* Discard packets with VID not enabled on the switch */ 1050 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 1051 1052 /* Discard packets with VID not enabled on the ingress port */ 1053 for (port = 0; port < dev->phy_port_cnt; ++port) 1054 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER, 1055 flag); 1056 1057 return 0; 1058 } 1059 1060 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state) 1061 { 1062 if (ksz_is_ksz88x3(dev)) { 1063 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID, 1064 0x03 << (4 - 2 * port), state); 1065 } else { 1066 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); 1067 } 1068 } 1069 1070 int ksz8_port_vlan_add(struct ksz_device *dev, int port, 1071 const struct switchdev_obj_port_vlan *vlan, 1072 struct netlink_ext_ack *extack) 1073 { 1074 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1075 struct ksz_port *p = &dev->ports[port]; 1076 u16 data, new_pvid = 0; 1077 u8 fid, member, valid; 1078 1079 if (ksz_is_ksz88x3(dev)) 1080 return -ENOTSUPP; 1081 1082 /* If a VLAN is added with untagged flag different from the 1083 * port's Remove Tag flag, we need to change the latter. 1084 * Ignore VID 0, which is always untagged. 1085 * Ignore CPU port, which will always be tagged. 1086 */ 1087 if (untagged != p->remove_tag && vlan->vid != 0 && 1088 port != dev->cpu_port) { 1089 unsigned int vid; 1090 1091 /* Reject attempts to add a VLAN that requires the 1092 * Remove Tag flag to be changed, unless there are no 1093 * other VLANs currently configured. 1094 */ 1095 for (vid = 1; vid < dev->info->num_vlans; ++vid) { 1096 /* Skip the VID we are going to add or reconfigure */ 1097 if (vid == vlan->vid) 1098 continue; 1099 1100 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0], 1101 &fid, &member, &valid); 1102 if (valid && (member & BIT(port))) 1103 return -EINVAL; 1104 } 1105 1106 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1107 p->remove_tag = untagged; 1108 } 1109 1110 ksz8_r_vlan_table(dev, vlan->vid, &data); 1111 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1112 1113 /* First time to setup the VLAN entry. */ 1114 if (!valid) { 1115 /* Need to find a way to map VID to FID. */ 1116 fid = 1; 1117 valid = 1; 1118 } 1119 member |= BIT(port); 1120 1121 ksz8_to_vlan(dev, fid, member, valid, &data); 1122 ksz8_w_vlan_table(dev, vlan->vid, data); 1123 1124 /* change PVID */ 1125 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1126 new_pvid = vlan->vid; 1127 1128 if (new_pvid) { 1129 u16 vid; 1130 1131 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1132 vid &= ~VLAN_VID_MASK; 1133 vid |= new_pvid; 1134 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1135 1136 ksz8_port_enable_pvid(dev, port, true); 1137 } 1138 1139 return 0; 1140 } 1141 1142 int ksz8_port_vlan_del(struct ksz_device *dev, int port, 1143 const struct switchdev_obj_port_vlan *vlan) 1144 { 1145 u16 data, pvid; 1146 u8 fid, member, valid; 1147 1148 if (ksz_is_ksz88x3(dev)) 1149 return -ENOTSUPP; 1150 1151 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1152 pvid = pvid & 0xFFF; 1153 1154 ksz8_r_vlan_table(dev, vlan->vid, &data); 1155 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1156 1157 member &= ~BIT(port); 1158 1159 /* Invalidate the entry if no more member. */ 1160 if (!member) { 1161 fid = 0; 1162 valid = 0; 1163 } 1164 1165 ksz8_to_vlan(dev, fid, member, valid, &data); 1166 ksz8_w_vlan_table(dev, vlan->vid, data); 1167 1168 if (pvid == vlan->vid) 1169 ksz8_port_enable_pvid(dev, port, false); 1170 1171 return 0; 1172 } 1173 1174 int ksz8_port_mirror_add(struct ksz_device *dev, int port, 1175 struct dsa_mall_mirror_tc_entry *mirror, 1176 bool ingress, struct netlink_ext_ack *extack) 1177 { 1178 if (ingress) { 1179 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1180 dev->mirror_rx |= BIT(port); 1181 } else { 1182 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1183 dev->mirror_tx |= BIT(port); 1184 } 1185 1186 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 1187 1188 /* configure mirror port */ 1189 if (dev->mirror_rx || dev->mirror_tx) 1190 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1191 PORT_MIRROR_SNIFFER, true); 1192 1193 return 0; 1194 } 1195 1196 void ksz8_port_mirror_del(struct ksz_device *dev, int port, 1197 struct dsa_mall_mirror_tc_entry *mirror) 1198 { 1199 u8 data; 1200 1201 if (mirror->ingress) { 1202 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1203 dev->mirror_rx &= ~BIT(port); 1204 } else { 1205 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1206 dev->mirror_tx &= ~BIT(port); 1207 } 1208 1209 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1210 1211 if (!dev->mirror_rx && !dev->mirror_tx) 1212 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1213 PORT_MIRROR_SNIFFER, false); 1214 } 1215 1216 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 1217 { 1218 struct ksz_port *p = &dev->ports[port]; 1219 u8 data8; 1220 1221 if (!p->interface && dev->compat_interface) { 1222 dev_warn(dev->dev, 1223 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1224 "Please update your device tree.\n", 1225 port); 1226 p->interface = dev->compat_interface; 1227 } 1228 1229 /* Configure MII interface for proper network communication. */ 1230 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8); 1231 data8 &= ~PORT_INTERFACE_TYPE; 1232 data8 &= ~PORT_GMII_1GPS_MODE; 1233 switch (p->interface) { 1234 case PHY_INTERFACE_MODE_MII: 1235 p->phydev.speed = SPEED_100; 1236 break; 1237 case PHY_INTERFACE_MODE_RMII: 1238 data8 |= PORT_INTERFACE_RMII; 1239 p->phydev.speed = SPEED_100; 1240 break; 1241 case PHY_INTERFACE_MODE_GMII: 1242 data8 |= PORT_GMII_1GPS_MODE; 1243 data8 |= PORT_INTERFACE_GMII; 1244 p->phydev.speed = SPEED_1000; 1245 break; 1246 default: 1247 data8 &= ~PORT_RGMII_ID_IN_ENABLE; 1248 data8 &= ~PORT_RGMII_ID_OUT_ENABLE; 1249 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1250 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1251 data8 |= PORT_RGMII_ID_IN_ENABLE; 1252 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1253 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1254 data8 |= PORT_RGMII_ID_OUT_ENABLE; 1255 data8 |= PORT_GMII_1GPS_MODE; 1256 data8 |= PORT_INTERFACE_RGMII; 1257 p->phydev.speed = SPEED_1000; 1258 break; 1259 } 1260 ksz_write8(dev, REG_PORT_5_CTRL_6, data8); 1261 p->phydev.duplex = 1; 1262 } 1263 1264 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1265 { 1266 struct dsa_switch *ds = dev->ds; 1267 struct ksz8 *ksz8 = dev->priv; 1268 const u32 *masks; 1269 u8 member; 1270 1271 masks = ksz8->masks; 1272 1273 /* enable broadcast storm limit */ 1274 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1275 1276 if (!ksz_is_ksz88x3(dev)) 1277 ksz8795_set_prio_queue(dev, port, 4); 1278 1279 /* disable DiffServ priority */ 1280 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false); 1281 1282 /* replace priority */ 1283 ksz_port_cfg(dev, port, P_802_1P_CTRL, 1284 masks[PORT_802_1P_REMAPPING], false); 1285 1286 /* enable 802.1p priority */ 1287 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true); 1288 1289 if (cpu_port) { 1290 if (!ksz_is_ksz88x3(dev)) 1291 ksz8795_cpu_interface_select(dev, port); 1292 1293 member = dsa_user_ports(ds); 1294 } else { 1295 member = BIT(dsa_upstream_port(ds, port)); 1296 } 1297 1298 ksz8_cfg_port_member(dev, port, member); 1299 } 1300 1301 void ksz8_config_cpu_port(struct dsa_switch *ds) 1302 { 1303 struct ksz_device *dev = ds->priv; 1304 struct ksz8 *ksz8 = dev->priv; 1305 const u8 *regs = ksz8->regs; 1306 struct ksz_port *p; 1307 const u32 *masks; 1308 u8 remote; 1309 int i; 1310 1311 masks = ksz8->masks; 1312 1313 /* Switch marks the maximum frame with extra byte as oversize. */ 1314 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true); 1315 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 1316 1317 p = &dev->ports[dev->cpu_port]; 1318 p->on = 1; 1319 1320 ksz8_port_setup(dev, dev->cpu_port, true); 1321 1322 for (i = 0; i < dev->phy_port_cnt; i++) { 1323 p = &dev->ports[i]; 1324 1325 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1326 1327 /* Last port may be disabled. */ 1328 if (i == dev->phy_port_cnt) 1329 break; 1330 p->on = 1; 1331 p->phy = 1; 1332 } 1333 for (i = 0; i < dev->phy_port_cnt; i++) { 1334 p = &dev->ports[i]; 1335 if (!p->on) 1336 continue; 1337 if (!ksz_is_ksz88x3(dev)) { 1338 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 1339 if (remote & KSZ8_PORT_FIBER_MODE) 1340 p->fiber = 1; 1341 } 1342 if (p->fiber) 1343 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL, 1344 true); 1345 else 1346 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL, 1347 false); 1348 } 1349 } 1350 1351 static int ksz8_handle_global_errata(struct dsa_switch *ds) 1352 { 1353 struct ksz_device *dev = ds->priv; 1354 int ret = 0; 1355 1356 /* KSZ87xx Errata DS80000687C. 1357 * Module 2: Link drops with some EEE link partners. 1358 * An issue with the EEE next page exchange between the 1359 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in 1360 * the link dropping. 1361 */ 1362 if (dev->info->ksz87xx_eee_link_erratum) 1363 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0); 1364 1365 return ret; 1366 } 1367 1368 int ksz8_enable_stp_addr(struct ksz_device *dev) 1369 { 1370 struct alu_struct alu; 1371 1372 /* Setup STP address for STP operation. */ 1373 memset(&alu, 0, sizeof(alu)); 1374 ether_addr_copy(alu.mac, eth_stp_addr); 1375 alu.is_static = true; 1376 alu.is_override = true; 1377 alu.port_forward = dev->info->cpu_ports; 1378 1379 ksz8_w_sta_mac_table(dev, 0, &alu); 1380 1381 return 0; 1382 } 1383 1384 int ksz8_setup(struct dsa_switch *ds) 1385 { 1386 struct ksz_device *dev = ds->priv; 1387 int i; 1388 1389 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true); 1390 1391 /* Enable automatic fast aging when link changed detected. */ 1392 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 1393 1394 /* Enable aggressive back off algorithm in half duplex mode. */ 1395 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1, 1396 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 1397 1398 /* 1399 * Make sure unicast VLAN boundary is set as default and 1400 * enable no excessive collision drop. 1401 */ 1402 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2, 1403 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 1404 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 1405 1406 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 1407 1408 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1409 1410 if (!ksz_is_ksz88x3(dev)) 1411 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); 1412 1413 for (i = 0; i < (dev->info->num_vlans / 4); i++) 1414 ksz8_r_vlan_entries(dev, i); 1415 1416 return ksz8_handle_global_errata(ds); 1417 } 1418 1419 void ksz8_get_caps(struct ksz_device *dev, int port, 1420 struct phylink_config *config) 1421 { 1422 config->mac_capabilities = MAC_10 | MAC_100; 1423 1424 /* Silicon Errata Sheet (DS80000830A): 1425 * "Port 1 does not respond to received flow control PAUSE frames" 1426 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3 1427 * switches. 1428 */ 1429 if (!ksz_is_ksz88x3(dev) || port) 1430 config->mac_capabilities |= MAC_SYM_PAUSE; 1431 1432 /* Asym pause is not supported on KSZ8863 and KSZ8873 */ 1433 if (!ksz_is_ksz88x3(dev)) 1434 config->mac_capabilities |= MAC_ASYM_PAUSE; 1435 } 1436 1437 u32 ksz8_get_port_addr(int port, int offset) 1438 { 1439 return PORT_CTRL_ADDR(port, offset); 1440 } 1441 1442 int ksz8_switch_init(struct ksz_device *dev) 1443 { 1444 struct ksz8 *ksz8 = dev->priv; 1445 1446 dev->cpu_port = fls(dev->info->cpu_ports) - 1; 1447 dev->phy_port_cnt = dev->info->port_cnt - 1; 1448 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports; 1449 1450 if (ksz_is_ksz88x3(dev)) { 1451 ksz8->regs = ksz8863_regs; 1452 ksz8->masks = ksz8863_masks; 1453 ksz8->shifts = ksz8863_shifts; 1454 } else { 1455 ksz8->regs = ksz8795_regs; 1456 ksz8->masks = ksz8795_masks; 1457 ksz8->shifts = ksz8795_shifts; 1458 } 1459 1460 /* We rely on software untagging on the CPU port, so that we 1461 * can support both tagged and untagged VLANs 1462 */ 1463 dev->ds->untag_bridge_pvid = true; 1464 1465 /* VLAN filtering is partly controlled by the global VLAN 1466 * Enable flag 1467 */ 1468 dev->ds->vlan_filtering_is_global = true; 1469 1470 return 0; 1471 } 1472 1473 void ksz8_switch_exit(struct ksz_device *dev) 1474 { 1475 ksz8_reset_switch(dev); 1476 } 1477 1478 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 1479 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 1480 MODULE_LICENSE("GPL"); 1481