sdhci.c (1650d0c71a209c7d6bdddda8a7e187c537ceb71a) sdhci.c (1771059cf5f9c09e37ef6315df8acf120f2642fc)
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at

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1107 pr_warn("%s: Invalid UHS-I mode selected\n",
1108 mmc_hostname(host->mmc));
1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1110 break;
1111 }
1112 return preset;
1113}
1114
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at

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1107 pr_warn("%s: Invalid UHS-I mode selected\n",
1108 mmc_hostname(host->mmc));
1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1110 break;
1111 }
1112 return preset;
1113}
1114
1115static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1115void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1116{
1117 int div = 0; /* Initialized for compiler warning */
1118 int real_div = div, clk_mul = 1;
1119 u16 clk = 0;
1120 unsigned long timeout;
1121
1116{
1117 int div = 0; /* Initialized for compiler warning */
1118 int real_div = div, clk_mul = 1;
1119 u16 clk = 0;
1120 unsigned long timeout;
1121
1122 if (host->ops->set_clock) {
1123 host->ops->set_clock(host, clock);
1124 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1125 return;
1126 }
1127
1128 host->mmc->actual_clock = 0;
1129
1130 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1131
1132 if (clock == 0)
1133 return;
1134
1135 if (host->version >= SDHCI_SPEC_300) {

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1216 }
1217 timeout--;
1218 mdelay(1);
1219 }
1220
1221 clk |= SDHCI_CLOCK_CARD_EN;
1222 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1223}
1122 host->mmc->actual_clock = 0;
1123
1124 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1125
1126 if (clock == 0)
1127 return;
1128
1129 if (host->version >= SDHCI_SPEC_300) {

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1210 }
1211 timeout--;
1212 mdelay(1);
1213 }
1214
1215 clk |= SDHCI_CLOCK_CARD_EN;
1216 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1217}
1218EXPORT_SYMBOL_GPL(sdhci_set_clock);
1224
1225static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1226{
1227 u8 pwr = 0;
1228
1229 if (power != (unsigned short)-1) {
1230 switch (1 << power) {
1231 case MMC_VDD_165_195:

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1434 }
1435
1436 if (host->version >= SDHCI_SPEC_300 &&
1437 (ios->power_mode == MMC_POWER_UP) &&
1438 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1439 sdhci_enable_preset_value(host, false);
1440
1441 if (!ios->clock || ios->clock != host->clock) {
1219
1220static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1221{
1222 u8 pwr = 0;
1223
1224 if (power != (unsigned short)-1) {
1225 switch (1 << power) {
1226 case MMC_VDD_165_195:

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1429 }
1430
1431 if (host->version >= SDHCI_SPEC_300 &&
1432 (ios->power_mode == MMC_POWER_UP) &&
1433 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1434 sdhci_enable_preset_value(host, false);
1435
1436 if (!ios->clock || ios->clock != host->clock) {
1442 sdhci_set_clock(host, ios->clock);
1437 host->ops->set_clock(host, ios->clock);
1443 host->clock = ios->clock;
1444 }
1445
1446 if (ios->power_mode == MMC_POWER_OFF)
1447 vdd_bit = sdhci_set_power(host, -1);
1448 else
1449 vdd_bit = sdhci_set_power(host, ios->vdd);
1450

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1505 /* Reset SD Clock Enable */
1506 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1507 clk &= ~SDHCI_CLOCK_CARD_EN;
1508 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1509
1510 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1511
1512 /* Re-enable SD Clock */
1438 host->clock = ios->clock;
1439 }
1440
1441 if (ios->power_mode == MMC_POWER_OFF)
1442 vdd_bit = sdhci_set_power(host, -1);
1443 else
1444 vdd_bit = sdhci_set_power(host, ios->vdd);
1445

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1500 /* Reset SD Clock Enable */
1501 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1502 clk &= ~SDHCI_CLOCK_CARD_EN;
1503 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1504
1505 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1506
1507 /* Re-enable SD Clock */
1513 sdhci_set_clock(host, host->clock);
1508 host->ops->set_clock(host, host->clock);
1514 }
1515
1516
1517 /* Reset SD Clock Enable */
1518 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1519 clk &= ~SDHCI_CLOCK_CARD_EN;
1520 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1521

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1550
1551 sdhci_enable_preset_value(host, true);
1552 preset = sdhci_get_preset_value(host);
1553 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1554 >> SDHCI_PRESET_DRV_SHIFT;
1555 }
1556
1557 /* Re-enable SD Clock */
1509 }
1510
1511
1512 /* Reset SD Clock Enable */
1513 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1514 clk &= ~SDHCI_CLOCK_CARD_EN;
1515 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1516

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1545
1546 sdhci_enable_preset_value(host, true);
1547 preset = sdhci_get_preset_value(host);
1548 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1549 >> SDHCI_PRESET_DRV_SHIFT;
1550 }
1551
1552 /* Re-enable SD Clock */
1558 sdhci_set_clock(host, host->clock);
1553 host->ops->set_clock(host, host->clock);
1559 } else
1560 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1561
1562 /*
1563 * Some (ENE) controllers go apeshit on some ios operation,
1564 * signalling timeout and CRC errors even on CMD0. Resetting
1565 * it on each ios seems to solve the problem.
1566 */

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2124 ((mrq->cmd && mrq->cmd->error) ||
2125 (mrq->data && (mrq->data->error ||
2126 (mrq->data->stop && mrq->data->stop->error))) ||
2127 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2128
2129 /* Some controllers need this kick or reset won't work here */
2130 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2131 /* This is to force an update */
1554 } else
1555 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1556
1557 /*
1558 * Some (ENE) controllers go apeshit on some ios operation,
1559 * signalling timeout and CRC errors even on CMD0. Resetting
1560 * it on each ios seems to solve the problem.
1561 */

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2119 ((mrq->cmd && mrq->cmd->error) ||
2120 (mrq->data && (mrq->data->error ||
2121 (mrq->data->stop && mrq->data->stop->error))) ||
2122 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2123
2124 /* Some controllers need this kick or reset won't work here */
2125 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2126 /* This is to force an update */
2132 sdhci_set_clock(host, host->clock);
2127 host->ops->set_clock(host, host->clock);
2133
2134 /* Spec says we should do both at the same time, but Ricoh
2135 controllers do not like that. */
2136 sdhci_do_reset(host, SDHCI_RESET_CMD);
2137 sdhci_do_reset(host, SDHCI_RESET_DATA);
2138 }
2139
2140 host->mrq = NULL;

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2129 /* Spec says we should do both at the same time, but Ricoh
2130 controllers do not like that. */
2131 sdhci_do_reset(host, SDHCI_RESET_CMD);
2132 sdhci_do_reset(host, SDHCI_RESET_DATA);
2133 }
2134
2135 host->mrq = NULL;

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