1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 26 #include <linux/leds.h> 27 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/slot-gpio.h> 32 33 #include "sdhci.h" 34 35 #define DRIVER_NAME "sdhci" 36 37 #define DBG(f, x...) \ 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 39 40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 41 defined(CONFIG_MMC_SDHCI_MODULE)) 42 #define SDHCI_USE_LEDS_CLASS 43 #endif 44 45 #define MAX_TUNING_LOOP 40 46 47 #define ADMA_SIZE ((128 * 2 + 1) * 4) 48 49 static unsigned int debug_quirks = 0; 50 static unsigned int debug_quirks2; 51 52 static void sdhci_finish_data(struct sdhci_host *); 53 54 static void sdhci_finish_command(struct sdhci_host *); 55 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 56 static void sdhci_tuning_timer(unsigned long data); 57 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 58 59 #ifdef CONFIG_PM_RUNTIME 60 static int sdhci_runtime_pm_get(struct sdhci_host *host); 61 static int sdhci_runtime_pm_put(struct sdhci_host *host); 62 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); 63 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); 64 #else 65 static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 66 { 67 return 0; 68 } 69 static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 70 { 71 return 0; 72 } 73 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 74 { 75 } 76 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 77 { 78 } 79 #endif 80 81 static void sdhci_dumpregs(struct sdhci_host *host) 82 { 83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 84 mmc_hostname(host->mmc)); 85 86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 87 sdhci_readl(host, SDHCI_DMA_ADDRESS), 88 sdhci_readw(host, SDHCI_HOST_VERSION)); 89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 90 sdhci_readw(host, SDHCI_BLOCK_SIZE), 91 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 93 sdhci_readl(host, SDHCI_ARGUMENT), 94 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 96 sdhci_readl(host, SDHCI_PRESENT_STATE), 97 sdhci_readb(host, SDHCI_HOST_CONTROL)); 98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 99 sdhci_readb(host, SDHCI_POWER_CONTROL), 100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 103 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 106 sdhci_readl(host, SDHCI_INT_STATUS)); 107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 108 sdhci_readl(host, SDHCI_INT_ENABLE), 109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 111 sdhci_readw(host, SDHCI_ACMD12_ERR), 112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 114 sdhci_readl(host, SDHCI_CAPABILITIES), 115 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 117 sdhci_readw(host, SDHCI_COMMAND), 118 sdhci_readl(host, SDHCI_MAX_CURRENT)); 119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 120 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 121 122 if (host->flags & SDHCI_USE_ADMA) 123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 124 readl(host->ioaddr + SDHCI_ADMA_ERROR), 125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 126 127 pr_debug(DRIVER_NAME ": ===========================================\n"); 128 } 129 130 /*****************************************************************************\ 131 * * 132 * Low level functions * 133 * * 134 \*****************************************************************************/ 135 136 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 137 { 138 u32 present; 139 140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 141 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 142 return; 143 144 if (enable) { 145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 146 SDHCI_CARD_PRESENT; 147 148 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 149 SDHCI_INT_CARD_INSERT; 150 } else { 151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 152 } 153 154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 156 } 157 158 static void sdhci_enable_card_detection(struct sdhci_host *host) 159 { 160 sdhci_set_card_detection(host, true); 161 } 162 163 static void sdhci_disable_card_detection(struct sdhci_host *host) 164 { 165 sdhci_set_card_detection(host, false); 166 } 167 168 void sdhci_reset(struct sdhci_host *host, u8 mask) 169 { 170 unsigned long timeout; 171 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 173 174 if (mask & SDHCI_RESET_ALL) { 175 host->clock = 0; 176 /* Reset-all turns off SD Bus Power */ 177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 178 sdhci_runtime_pm_bus_off(host); 179 } 180 181 /* Wait max 100 ms */ 182 timeout = 100; 183 184 /* hw clears the bit when it's done */ 185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 186 if (timeout == 0) { 187 pr_err("%s: Reset 0x%x never completed.\n", 188 mmc_hostname(host->mmc), (int)mask); 189 sdhci_dumpregs(host); 190 return; 191 } 192 timeout--; 193 mdelay(1); 194 } 195 } 196 EXPORT_SYMBOL_GPL(sdhci_reset); 197 198 static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 199 { 200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 202 SDHCI_CARD_PRESENT)) 203 return; 204 } 205 206 host->ops->reset(host, mask); 207 208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 209 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL)) 210 host->ops->enable_dma(host); 211 } 212 } 213 214 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 215 216 static void sdhci_init(struct sdhci_host *host, int soft) 217 { 218 if (soft) 219 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 220 else 221 sdhci_do_reset(host, SDHCI_RESET_ALL); 222 223 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 224 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 225 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 226 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 227 SDHCI_INT_RESPONSE; 228 229 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 230 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 231 232 if (soft) { 233 /* force clock reconfiguration */ 234 host->clock = 0; 235 sdhci_set_ios(host->mmc, &host->mmc->ios); 236 } 237 } 238 239 static void sdhci_reinit(struct sdhci_host *host) 240 { 241 sdhci_init(host, 0); 242 /* 243 * Retuning stuffs are affected by different cards inserted and only 244 * applicable to UHS-I cards. So reset these fields to their initial 245 * value when card is removed. 246 */ 247 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 248 host->flags &= ~SDHCI_USING_RETUNING_TIMER; 249 250 del_timer_sync(&host->tuning_timer); 251 host->flags &= ~SDHCI_NEEDS_RETUNING; 252 host->mmc->max_blk_count = 253 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 254 } 255 sdhci_enable_card_detection(host); 256 } 257 258 static void sdhci_activate_led(struct sdhci_host *host) 259 { 260 u8 ctrl; 261 262 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 263 ctrl |= SDHCI_CTRL_LED; 264 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 265 } 266 267 static void sdhci_deactivate_led(struct sdhci_host *host) 268 { 269 u8 ctrl; 270 271 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 272 ctrl &= ~SDHCI_CTRL_LED; 273 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 274 } 275 276 #ifdef SDHCI_USE_LEDS_CLASS 277 static void sdhci_led_control(struct led_classdev *led, 278 enum led_brightness brightness) 279 { 280 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 281 unsigned long flags; 282 283 spin_lock_irqsave(&host->lock, flags); 284 285 if (host->runtime_suspended) 286 goto out; 287 288 if (brightness == LED_OFF) 289 sdhci_deactivate_led(host); 290 else 291 sdhci_activate_led(host); 292 out: 293 spin_unlock_irqrestore(&host->lock, flags); 294 } 295 #endif 296 297 /*****************************************************************************\ 298 * * 299 * Core functions * 300 * * 301 \*****************************************************************************/ 302 303 static void sdhci_read_block_pio(struct sdhci_host *host) 304 { 305 unsigned long flags; 306 size_t blksize, len, chunk; 307 u32 uninitialized_var(scratch); 308 u8 *buf; 309 310 DBG("PIO reading\n"); 311 312 blksize = host->data->blksz; 313 chunk = 0; 314 315 local_irq_save(flags); 316 317 while (blksize) { 318 if (!sg_miter_next(&host->sg_miter)) 319 BUG(); 320 321 len = min(host->sg_miter.length, blksize); 322 323 blksize -= len; 324 host->sg_miter.consumed = len; 325 326 buf = host->sg_miter.addr; 327 328 while (len) { 329 if (chunk == 0) { 330 scratch = sdhci_readl(host, SDHCI_BUFFER); 331 chunk = 4; 332 } 333 334 *buf = scratch & 0xFF; 335 336 buf++; 337 scratch >>= 8; 338 chunk--; 339 len--; 340 } 341 } 342 343 sg_miter_stop(&host->sg_miter); 344 345 local_irq_restore(flags); 346 } 347 348 static void sdhci_write_block_pio(struct sdhci_host *host) 349 { 350 unsigned long flags; 351 size_t blksize, len, chunk; 352 u32 scratch; 353 u8 *buf; 354 355 DBG("PIO writing\n"); 356 357 blksize = host->data->blksz; 358 chunk = 0; 359 scratch = 0; 360 361 local_irq_save(flags); 362 363 while (blksize) { 364 if (!sg_miter_next(&host->sg_miter)) 365 BUG(); 366 367 len = min(host->sg_miter.length, blksize); 368 369 blksize -= len; 370 host->sg_miter.consumed = len; 371 372 buf = host->sg_miter.addr; 373 374 while (len) { 375 scratch |= (u32)*buf << (chunk * 8); 376 377 buf++; 378 chunk++; 379 len--; 380 381 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 382 sdhci_writel(host, scratch, SDHCI_BUFFER); 383 chunk = 0; 384 scratch = 0; 385 } 386 } 387 } 388 389 sg_miter_stop(&host->sg_miter); 390 391 local_irq_restore(flags); 392 } 393 394 static void sdhci_transfer_pio(struct sdhci_host *host) 395 { 396 u32 mask; 397 398 BUG_ON(!host->data); 399 400 if (host->blocks == 0) 401 return; 402 403 if (host->data->flags & MMC_DATA_READ) 404 mask = SDHCI_DATA_AVAILABLE; 405 else 406 mask = SDHCI_SPACE_AVAILABLE; 407 408 /* 409 * Some controllers (JMicron JMB38x) mess up the buffer bits 410 * for transfers < 4 bytes. As long as it is just one block, 411 * we can ignore the bits. 412 */ 413 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 414 (host->data->blocks == 1)) 415 mask = ~0; 416 417 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 418 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 419 udelay(100); 420 421 if (host->data->flags & MMC_DATA_READ) 422 sdhci_read_block_pio(host); 423 else 424 sdhci_write_block_pio(host); 425 426 host->blocks--; 427 if (host->blocks == 0) 428 break; 429 } 430 431 DBG("PIO transfer complete.\n"); 432 } 433 434 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 435 { 436 local_irq_save(*flags); 437 return kmap_atomic(sg_page(sg)) + sg->offset; 438 } 439 440 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 441 { 442 kunmap_atomic(buffer); 443 local_irq_restore(*flags); 444 } 445 446 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 447 { 448 __le32 *dataddr = (__le32 __force *)(desc + 4); 449 __le16 *cmdlen = (__le16 __force *)desc; 450 451 /* SDHCI specification says ADMA descriptors should be 4 byte 452 * aligned, so using 16 or 32bit operations should be safe. */ 453 454 cmdlen[0] = cpu_to_le16(cmd); 455 cmdlen[1] = cpu_to_le16(len); 456 457 dataddr[0] = cpu_to_le32(addr); 458 } 459 460 static int sdhci_adma_table_pre(struct sdhci_host *host, 461 struct mmc_data *data) 462 { 463 int direction; 464 465 u8 *desc; 466 u8 *align; 467 dma_addr_t addr; 468 dma_addr_t align_addr; 469 int len, offset; 470 471 struct scatterlist *sg; 472 int i; 473 char *buffer; 474 unsigned long flags; 475 476 /* 477 * The spec does not specify endianness of descriptor table. 478 * We currently guess that it is LE. 479 */ 480 481 if (data->flags & MMC_DATA_READ) 482 direction = DMA_FROM_DEVICE; 483 else 484 direction = DMA_TO_DEVICE; 485 486 host->align_addr = dma_map_single(mmc_dev(host->mmc), 487 host->align_buffer, 128 * 4, direction); 488 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 489 goto fail; 490 BUG_ON(host->align_addr & 0x3); 491 492 host->sg_count = dma_map_sg(mmc_dev(host->mmc), 493 data->sg, data->sg_len, direction); 494 if (host->sg_count == 0) 495 goto unmap_align; 496 497 desc = host->adma_desc; 498 align = host->align_buffer; 499 500 align_addr = host->align_addr; 501 502 for_each_sg(data->sg, sg, host->sg_count, i) { 503 addr = sg_dma_address(sg); 504 len = sg_dma_len(sg); 505 506 /* 507 * The SDHCI specification states that ADMA 508 * addresses must be 32-bit aligned. If they 509 * aren't, then we use a bounce buffer for 510 * the (up to three) bytes that screw up the 511 * alignment. 512 */ 513 offset = (4 - (addr & 0x3)) & 0x3; 514 if (offset) { 515 if (data->flags & MMC_DATA_WRITE) { 516 buffer = sdhci_kmap_atomic(sg, &flags); 517 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 518 memcpy(align, buffer, offset); 519 sdhci_kunmap_atomic(buffer, &flags); 520 } 521 522 /* tran, valid */ 523 sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 524 525 BUG_ON(offset > 65536); 526 527 align += 4; 528 align_addr += 4; 529 530 desc += 8; 531 532 addr += offset; 533 len -= offset; 534 } 535 536 BUG_ON(len > 65536); 537 538 /* tran, valid */ 539 sdhci_set_adma_desc(desc, addr, len, 0x21); 540 desc += 8; 541 542 /* 543 * If this triggers then we have a calculation bug 544 * somewhere. :/ 545 */ 546 WARN_ON((desc - host->adma_desc) > ADMA_SIZE); 547 } 548 549 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 550 /* 551 * Mark the last descriptor as the terminating descriptor 552 */ 553 if (desc != host->adma_desc) { 554 desc -= 8; 555 desc[0] |= 0x2; /* end */ 556 } 557 } else { 558 /* 559 * Add a terminating entry. 560 */ 561 562 /* nop, end, valid */ 563 sdhci_set_adma_desc(desc, 0, 0, 0x3); 564 } 565 566 /* 567 * Resync align buffer as we might have changed it. 568 */ 569 if (data->flags & MMC_DATA_WRITE) { 570 dma_sync_single_for_device(mmc_dev(host->mmc), 571 host->align_addr, 128 * 4, direction); 572 } 573 574 return 0; 575 576 unmap_align: 577 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 578 128 * 4, direction); 579 fail: 580 return -EINVAL; 581 } 582 583 static void sdhci_adma_table_post(struct sdhci_host *host, 584 struct mmc_data *data) 585 { 586 int direction; 587 588 struct scatterlist *sg; 589 int i, size; 590 u8 *align; 591 char *buffer; 592 unsigned long flags; 593 bool has_unaligned; 594 595 if (data->flags & MMC_DATA_READ) 596 direction = DMA_FROM_DEVICE; 597 else 598 direction = DMA_TO_DEVICE; 599 600 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 601 128 * 4, direction); 602 603 /* Do a quick scan of the SG list for any unaligned mappings */ 604 has_unaligned = false; 605 for_each_sg(data->sg, sg, host->sg_count, i) 606 if (sg_dma_address(sg) & 3) { 607 has_unaligned = true; 608 break; 609 } 610 611 if (has_unaligned && data->flags & MMC_DATA_READ) { 612 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 613 data->sg_len, direction); 614 615 align = host->align_buffer; 616 617 for_each_sg(data->sg, sg, host->sg_count, i) { 618 if (sg_dma_address(sg) & 0x3) { 619 size = 4 - (sg_dma_address(sg) & 0x3); 620 621 buffer = sdhci_kmap_atomic(sg, &flags); 622 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 623 memcpy(buffer, align, size); 624 sdhci_kunmap_atomic(buffer, &flags); 625 626 align += 4; 627 } 628 } 629 } 630 631 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 632 data->sg_len, direction); 633 } 634 635 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 636 { 637 u8 count; 638 struct mmc_data *data = cmd->data; 639 unsigned target_timeout, current_timeout; 640 641 /* 642 * If the host controller provides us with an incorrect timeout 643 * value, just skip the check and use 0xE. The hardware may take 644 * longer to time out, but that's much better than having a too-short 645 * timeout value. 646 */ 647 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 648 return 0xE; 649 650 /* Unspecified timeout, assume max */ 651 if (!data && !cmd->busy_timeout) 652 return 0xE; 653 654 /* timeout in us */ 655 if (!data) 656 target_timeout = cmd->busy_timeout * 1000; 657 else { 658 target_timeout = data->timeout_ns / 1000; 659 if (host->clock) 660 target_timeout += data->timeout_clks / host->clock; 661 } 662 663 /* 664 * Figure out needed cycles. 665 * We do this in steps in order to fit inside a 32 bit int. 666 * The first step is the minimum timeout, which will have a 667 * minimum resolution of 6 bits: 668 * (1) 2^13*1000 > 2^22, 669 * (2) host->timeout_clk < 2^16 670 * => 671 * (1) / (2) > 2^6 672 */ 673 count = 0; 674 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 675 while (current_timeout < target_timeout) { 676 count++; 677 current_timeout <<= 1; 678 if (count >= 0xF) 679 break; 680 } 681 682 if (count >= 0xF) { 683 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 684 mmc_hostname(host->mmc), count, cmd->opcode); 685 count = 0xE; 686 } 687 688 return count; 689 } 690 691 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 692 { 693 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 694 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 695 696 if (host->flags & SDHCI_REQ_USE_DMA) 697 host->ier = (host->ier & ~pio_irqs) | dma_irqs; 698 else 699 host->ier = (host->ier & ~dma_irqs) | pio_irqs; 700 701 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 702 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 703 } 704 705 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 706 { 707 u8 count; 708 u8 ctrl; 709 struct mmc_data *data = cmd->data; 710 int ret; 711 712 WARN_ON(host->data); 713 714 if (data || (cmd->flags & MMC_RSP_BUSY)) { 715 count = sdhci_calc_timeout(host, cmd); 716 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 717 } 718 719 if (!data) 720 return; 721 722 /* Sanity checks */ 723 BUG_ON(data->blksz * data->blocks > 524288); 724 BUG_ON(data->blksz > host->mmc->max_blk_size); 725 BUG_ON(data->blocks > 65535); 726 727 host->data = data; 728 host->data_early = 0; 729 host->data->bytes_xfered = 0; 730 731 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 732 host->flags |= SDHCI_REQ_USE_DMA; 733 734 /* 735 * FIXME: This doesn't account for merging when mapping the 736 * scatterlist. 737 */ 738 if (host->flags & SDHCI_REQ_USE_DMA) { 739 int broken, i; 740 struct scatterlist *sg; 741 742 broken = 0; 743 if (host->flags & SDHCI_USE_ADMA) { 744 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 745 broken = 1; 746 } else { 747 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 748 broken = 1; 749 } 750 751 if (unlikely(broken)) { 752 for_each_sg(data->sg, sg, data->sg_len, i) { 753 if (sg->length & 0x3) { 754 DBG("Reverting to PIO because of " 755 "transfer size (%d)\n", 756 sg->length); 757 host->flags &= ~SDHCI_REQ_USE_DMA; 758 break; 759 } 760 } 761 } 762 } 763 764 /* 765 * The assumption here being that alignment is the same after 766 * translation to device address space. 767 */ 768 if (host->flags & SDHCI_REQ_USE_DMA) { 769 int broken, i; 770 struct scatterlist *sg; 771 772 broken = 0; 773 if (host->flags & SDHCI_USE_ADMA) { 774 /* 775 * As we use 3 byte chunks to work around 776 * alignment problems, we need to check this 777 * quirk. 778 */ 779 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 780 broken = 1; 781 } else { 782 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 783 broken = 1; 784 } 785 786 if (unlikely(broken)) { 787 for_each_sg(data->sg, sg, data->sg_len, i) { 788 if (sg->offset & 0x3) { 789 DBG("Reverting to PIO because of " 790 "bad alignment\n"); 791 host->flags &= ~SDHCI_REQ_USE_DMA; 792 break; 793 } 794 } 795 } 796 } 797 798 if (host->flags & SDHCI_REQ_USE_DMA) { 799 if (host->flags & SDHCI_USE_ADMA) { 800 ret = sdhci_adma_table_pre(host, data); 801 if (ret) { 802 /* 803 * This only happens when someone fed 804 * us an invalid request. 805 */ 806 WARN_ON(1); 807 host->flags &= ~SDHCI_REQ_USE_DMA; 808 } else { 809 sdhci_writel(host, host->adma_addr, 810 SDHCI_ADMA_ADDRESS); 811 } 812 } else { 813 int sg_cnt; 814 815 sg_cnt = dma_map_sg(mmc_dev(host->mmc), 816 data->sg, data->sg_len, 817 (data->flags & MMC_DATA_READ) ? 818 DMA_FROM_DEVICE : 819 DMA_TO_DEVICE); 820 if (sg_cnt == 0) { 821 /* 822 * This only happens when someone fed 823 * us an invalid request. 824 */ 825 WARN_ON(1); 826 host->flags &= ~SDHCI_REQ_USE_DMA; 827 } else { 828 WARN_ON(sg_cnt != 1); 829 sdhci_writel(host, sg_dma_address(data->sg), 830 SDHCI_DMA_ADDRESS); 831 } 832 } 833 } 834 835 /* 836 * Always adjust the DMA selection as some controllers 837 * (e.g. JMicron) can't do PIO properly when the selection 838 * is ADMA. 839 */ 840 if (host->version >= SDHCI_SPEC_200) { 841 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 842 ctrl &= ~SDHCI_CTRL_DMA_MASK; 843 if ((host->flags & SDHCI_REQ_USE_DMA) && 844 (host->flags & SDHCI_USE_ADMA)) 845 ctrl |= SDHCI_CTRL_ADMA32; 846 else 847 ctrl |= SDHCI_CTRL_SDMA; 848 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 849 } 850 851 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 852 int flags; 853 854 flags = SG_MITER_ATOMIC; 855 if (host->data->flags & MMC_DATA_READ) 856 flags |= SG_MITER_TO_SG; 857 else 858 flags |= SG_MITER_FROM_SG; 859 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 860 host->blocks = data->blocks; 861 } 862 863 sdhci_set_transfer_irqs(host); 864 865 /* Set the DMA boundary value and block size */ 866 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 867 data->blksz), SDHCI_BLOCK_SIZE); 868 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 869 } 870 871 static void sdhci_set_transfer_mode(struct sdhci_host *host, 872 struct mmc_command *cmd) 873 { 874 u16 mode; 875 struct mmc_data *data = cmd->data; 876 877 if (data == NULL) { 878 /* clear Auto CMD settings for no data CMDs */ 879 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 880 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 881 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 882 return; 883 } 884 885 WARN_ON(!host->data); 886 887 mode = SDHCI_TRNS_BLK_CNT_EN; 888 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 889 mode |= SDHCI_TRNS_MULTI; 890 /* 891 * If we are sending CMD23, CMD12 never gets sent 892 * on successful completion (so no Auto-CMD12). 893 */ 894 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 895 mode |= SDHCI_TRNS_AUTO_CMD12; 896 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 897 mode |= SDHCI_TRNS_AUTO_CMD23; 898 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 899 } 900 } 901 902 if (data->flags & MMC_DATA_READ) 903 mode |= SDHCI_TRNS_READ; 904 if (host->flags & SDHCI_REQ_USE_DMA) 905 mode |= SDHCI_TRNS_DMA; 906 907 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 908 } 909 910 static void sdhci_finish_data(struct sdhci_host *host) 911 { 912 struct mmc_data *data; 913 914 BUG_ON(!host->data); 915 916 data = host->data; 917 host->data = NULL; 918 919 if (host->flags & SDHCI_REQ_USE_DMA) { 920 if (host->flags & SDHCI_USE_ADMA) 921 sdhci_adma_table_post(host, data); 922 else { 923 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 924 data->sg_len, (data->flags & MMC_DATA_READ) ? 925 DMA_FROM_DEVICE : DMA_TO_DEVICE); 926 } 927 } 928 929 /* 930 * The specification states that the block count register must 931 * be updated, but it does not specify at what point in the 932 * data flow. That makes the register entirely useless to read 933 * back so we have to assume that nothing made it to the card 934 * in the event of an error. 935 */ 936 if (data->error) 937 data->bytes_xfered = 0; 938 else 939 data->bytes_xfered = data->blksz * data->blocks; 940 941 /* 942 * Need to send CMD12 if - 943 * a) open-ended multiblock transfer (no CMD23) 944 * b) error in multiblock transfer 945 */ 946 if (data->stop && 947 (data->error || 948 !host->mrq->sbc)) { 949 950 /* 951 * The controller needs a reset of internal state machines 952 * upon error conditions. 953 */ 954 if (data->error) { 955 sdhci_do_reset(host, SDHCI_RESET_CMD); 956 sdhci_do_reset(host, SDHCI_RESET_DATA); 957 } 958 959 sdhci_send_command(host, data->stop); 960 } else 961 tasklet_schedule(&host->finish_tasklet); 962 } 963 964 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 965 { 966 int flags; 967 u32 mask; 968 unsigned long timeout; 969 970 WARN_ON(host->cmd); 971 972 /* Wait max 10 ms */ 973 timeout = 10; 974 975 mask = SDHCI_CMD_INHIBIT; 976 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 977 mask |= SDHCI_DATA_INHIBIT; 978 979 /* We shouldn't wait for data inihibit for stop commands, even 980 though they might use busy signaling */ 981 if (host->mrq->data && (cmd == host->mrq->data->stop)) 982 mask &= ~SDHCI_DATA_INHIBIT; 983 984 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 985 if (timeout == 0) { 986 pr_err("%s: Controller never released " 987 "inhibit bit(s).\n", mmc_hostname(host->mmc)); 988 sdhci_dumpregs(host); 989 cmd->error = -EIO; 990 tasklet_schedule(&host->finish_tasklet); 991 return; 992 } 993 timeout--; 994 mdelay(1); 995 } 996 997 timeout = jiffies; 998 if (!cmd->data && cmd->busy_timeout > 9000) 999 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1000 else 1001 timeout += 10 * HZ; 1002 mod_timer(&host->timer, timeout); 1003 1004 host->cmd = cmd; 1005 1006 sdhci_prepare_data(host, cmd); 1007 1008 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1009 1010 sdhci_set_transfer_mode(host, cmd); 1011 1012 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1013 pr_err("%s: Unsupported response type!\n", 1014 mmc_hostname(host->mmc)); 1015 cmd->error = -EINVAL; 1016 tasklet_schedule(&host->finish_tasklet); 1017 return; 1018 } 1019 1020 if (!(cmd->flags & MMC_RSP_PRESENT)) 1021 flags = SDHCI_CMD_RESP_NONE; 1022 else if (cmd->flags & MMC_RSP_136) 1023 flags = SDHCI_CMD_RESP_LONG; 1024 else if (cmd->flags & MMC_RSP_BUSY) 1025 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1026 else 1027 flags = SDHCI_CMD_RESP_SHORT; 1028 1029 if (cmd->flags & MMC_RSP_CRC) 1030 flags |= SDHCI_CMD_CRC; 1031 if (cmd->flags & MMC_RSP_OPCODE) 1032 flags |= SDHCI_CMD_INDEX; 1033 1034 /* CMD19 is special in that the Data Present Select should be set */ 1035 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1036 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1037 flags |= SDHCI_CMD_DATA; 1038 1039 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1040 } 1041 EXPORT_SYMBOL_GPL(sdhci_send_command); 1042 1043 static void sdhci_finish_command(struct sdhci_host *host) 1044 { 1045 int i; 1046 1047 BUG_ON(host->cmd == NULL); 1048 1049 if (host->cmd->flags & MMC_RSP_PRESENT) { 1050 if (host->cmd->flags & MMC_RSP_136) { 1051 /* CRC is stripped so we need to do some shifting. */ 1052 for (i = 0;i < 4;i++) { 1053 host->cmd->resp[i] = sdhci_readl(host, 1054 SDHCI_RESPONSE + (3-i)*4) << 8; 1055 if (i != 3) 1056 host->cmd->resp[i] |= 1057 sdhci_readb(host, 1058 SDHCI_RESPONSE + (3-i)*4-1); 1059 } 1060 } else { 1061 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1062 } 1063 } 1064 1065 host->cmd->error = 0; 1066 1067 /* Finished CMD23, now send actual command. */ 1068 if (host->cmd == host->mrq->sbc) { 1069 host->cmd = NULL; 1070 sdhci_send_command(host, host->mrq->cmd); 1071 } else { 1072 1073 /* Processed actual command. */ 1074 if (host->data && host->data_early) 1075 sdhci_finish_data(host); 1076 1077 if (!host->cmd->data) 1078 tasklet_schedule(&host->finish_tasklet); 1079 1080 host->cmd = NULL; 1081 } 1082 } 1083 1084 static u16 sdhci_get_preset_value(struct sdhci_host *host) 1085 { 1086 u16 ctrl, preset = 0; 1087 1088 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1089 1090 switch (ctrl & SDHCI_CTRL_UHS_MASK) { 1091 case SDHCI_CTRL_UHS_SDR12: 1092 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1093 break; 1094 case SDHCI_CTRL_UHS_SDR25: 1095 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1096 break; 1097 case SDHCI_CTRL_UHS_SDR50: 1098 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1099 break; 1100 case SDHCI_CTRL_UHS_SDR104: 1101 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1102 break; 1103 case SDHCI_CTRL_UHS_DDR50: 1104 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1105 break; 1106 default: 1107 pr_warn("%s: Invalid UHS-I mode selected\n", 1108 mmc_hostname(host->mmc)); 1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1110 break; 1111 } 1112 return preset; 1113 } 1114 1115 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1116 { 1117 int div = 0; /* Initialized for compiler warning */ 1118 int real_div = div, clk_mul = 1; 1119 u16 clk = 0; 1120 unsigned long timeout; 1121 1122 if (host->ops->set_clock) { 1123 host->ops->set_clock(host, clock); 1124 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) 1125 return; 1126 } 1127 1128 host->mmc->actual_clock = 0; 1129 1130 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1131 1132 if (clock == 0) 1133 return; 1134 1135 if (host->version >= SDHCI_SPEC_300) { 1136 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) & 1137 SDHCI_CTRL_PRESET_VAL_ENABLE) { 1138 u16 pre_val; 1139 1140 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1141 pre_val = sdhci_get_preset_value(host); 1142 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1143 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1144 if (host->clk_mul && 1145 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1146 clk = SDHCI_PROG_CLOCK_MODE; 1147 real_div = div + 1; 1148 clk_mul = host->clk_mul; 1149 } else { 1150 real_div = max_t(int, 1, div << 1); 1151 } 1152 goto clock_set; 1153 } 1154 1155 /* 1156 * Check if the Host Controller supports Programmable Clock 1157 * Mode. 1158 */ 1159 if (host->clk_mul) { 1160 for (div = 1; div <= 1024; div++) { 1161 if ((host->max_clk * host->clk_mul / div) 1162 <= clock) 1163 break; 1164 } 1165 /* 1166 * Set Programmable Clock Mode in the Clock 1167 * Control register. 1168 */ 1169 clk = SDHCI_PROG_CLOCK_MODE; 1170 real_div = div; 1171 clk_mul = host->clk_mul; 1172 div--; 1173 } else { 1174 /* Version 3.00 divisors must be a multiple of 2. */ 1175 if (host->max_clk <= clock) 1176 div = 1; 1177 else { 1178 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1179 div += 2) { 1180 if ((host->max_clk / div) <= clock) 1181 break; 1182 } 1183 } 1184 real_div = div; 1185 div >>= 1; 1186 } 1187 } else { 1188 /* Version 2.00 divisors must be a power of 2. */ 1189 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1190 if ((host->max_clk / div) <= clock) 1191 break; 1192 } 1193 real_div = div; 1194 div >>= 1; 1195 } 1196 1197 clock_set: 1198 if (real_div) 1199 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1200 1201 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1202 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1203 << SDHCI_DIVIDER_HI_SHIFT; 1204 clk |= SDHCI_CLOCK_INT_EN; 1205 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1206 1207 /* Wait max 20 ms */ 1208 timeout = 20; 1209 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1210 & SDHCI_CLOCK_INT_STABLE)) { 1211 if (timeout == 0) { 1212 pr_err("%s: Internal clock never " 1213 "stabilised.\n", mmc_hostname(host->mmc)); 1214 sdhci_dumpregs(host); 1215 return; 1216 } 1217 timeout--; 1218 mdelay(1); 1219 } 1220 1221 clk |= SDHCI_CLOCK_CARD_EN; 1222 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1223 } 1224 1225 static int sdhci_set_power(struct sdhci_host *host, unsigned short power) 1226 { 1227 u8 pwr = 0; 1228 1229 if (power != (unsigned short)-1) { 1230 switch (1 << power) { 1231 case MMC_VDD_165_195: 1232 pwr = SDHCI_POWER_180; 1233 break; 1234 case MMC_VDD_29_30: 1235 case MMC_VDD_30_31: 1236 pwr = SDHCI_POWER_300; 1237 break; 1238 case MMC_VDD_32_33: 1239 case MMC_VDD_33_34: 1240 pwr = SDHCI_POWER_330; 1241 break; 1242 default: 1243 BUG(); 1244 } 1245 } 1246 1247 if (host->pwr == pwr) 1248 return -1; 1249 1250 host->pwr = pwr; 1251 1252 if (pwr == 0) { 1253 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1254 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1255 sdhci_runtime_pm_bus_off(host); 1256 return 0; 1257 } 1258 1259 /* 1260 * Spec says that we should clear the power reg before setting 1261 * a new value. Some controllers don't seem to like this though. 1262 */ 1263 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1264 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1265 1266 /* 1267 * At least the Marvell CaFe chip gets confused if we set the voltage 1268 * and set turn on power at the same time, so set the voltage first. 1269 */ 1270 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1271 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1272 1273 pwr |= SDHCI_POWER_ON; 1274 1275 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1276 1277 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1278 sdhci_runtime_pm_bus_on(host); 1279 1280 /* 1281 * Some controllers need an extra 10ms delay of 10ms before they 1282 * can apply clock after applying power 1283 */ 1284 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1285 mdelay(10); 1286 1287 return power; 1288 } 1289 1290 /*****************************************************************************\ 1291 * * 1292 * MMC callbacks * 1293 * * 1294 \*****************************************************************************/ 1295 1296 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1297 { 1298 struct sdhci_host *host; 1299 int present; 1300 unsigned long flags; 1301 u32 tuning_opcode; 1302 1303 host = mmc_priv(mmc); 1304 1305 sdhci_runtime_pm_get(host); 1306 1307 spin_lock_irqsave(&host->lock, flags); 1308 1309 WARN_ON(host->mrq != NULL); 1310 1311 #ifndef SDHCI_USE_LEDS_CLASS 1312 sdhci_activate_led(host); 1313 #endif 1314 1315 /* 1316 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1317 * requests if Auto-CMD12 is enabled. 1318 */ 1319 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1320 if (mrq->stop) { 1321 mrq->data->stop = NULL; 1322 mrq->stop = NULL; 1323 } 1324 } 1325 1326 host->mrq = mrq; 1327 1328 /* 1329 * Firstly check card presence from cd-gpio. The return could 1330 * be one of the following possibilities: 1331 * negative: cd-gpio is not available 1332 * zero: cd-gpio is used, and card is removed 1333 * one: cd-gpio is used, and card is present 1334 */ 1335 present = mmc_gpio_get_cd(host->mmc); 1336 if (present < 0) { 1337 /* If polling, assume that the card is always present. */ 1338 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1339 present = 1; 1340 else 1341 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 1342 SDHCI_CARD_PRESENT; 1343 } 1344 1345 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1346 host->mrq->cmd->error = -ENOMEDIUM; 1347 tasklet_schedule(&host->finish_tasklet); 1348 } else { 1349 u32 present_state; 1350 1351 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1352 /* 1353 * Check if the re-tuning timer has already expired and there 1354 * is no on-going data transfer. If so, we need to execute 1355 * tuning procedure before sending command. 1356 */ 1357 if ((host->flags & SDHCI_NEEDS_RETUNING) && 1358 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { 1359 if (mmc->card) { 1360 /* eMMC uses cmd21 but sd and sdio use cmd19 */ 1361 tuning_opcode = 1362 mmc->card->type == MMC_TYPE_MMC ? 1363 MMC_SEND_TUNING_BLOCK_HS200 : 1364 MMC_SEND_TUNING_BLOCK; 1365 1366 /* Here we need to set the host->mrq to NULL, 1367 * in case the pending finish_tasklet 1368 * finishes it incorrectly. 1369 */ 1370 host->mrq = NULL; 1371 1372 spin_unlock_irqrestore(&host->lock, flags); 1373 sdhci_execute_tuning(mmc, tuning_opcode); 1374 spin_lock_irqsave(&host->lock, flags); 1375 1376 /* Restore original mmc_request structure */ 1377 host->mrq = mrq; 1378 } 1379 } 1380 1381 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1382 sdhci_send_command(host, mrq->sbc); 1383 else 1384 sdhci_send_command(host, mrq->cmd); 1385 } 1386 1387 mmiowb(); 1388 spin_unlock_irqrestore(&host->lock, flags); 1389 } 1390 1391 void sdhci_set_bus_width(struct sdhci_host *host, int width) 1392 { 1393 u8 ctrl; 1394 1395 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1396 if (width == MMC_BUS_WIDTH_8) { 1397 ctrl &= ~SDHCI_CTRL_4BITBUS; 1398 if (host->version >= SDHCI_SPEC_300) 1399 ctrl |= SDHCI_CTRL_8BITBUS; 1400 } else { 1401 if (host->version >= SDHCI_SPEC_300) 1402 ctrl &= ~SDHCI_CTRL_8BITBUS; 1403 if (width == MMC_BUS_WIDTH_4) 1404 ctrl |= SDHCI_CTRL_4BITBUS; 1405 else 1406 ctrl &= ~SDHCI_CTRL_4BITBUS; 1407 } 1408 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1409 } 1410 EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 1411 1412 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 1413 { 1414 unsigned long flags; 1415 int vdd_bit = -1; 1416 u8 ctrl; 1417 1418 spin_lock_irqsave(&host->lock, flags); 1419 1420 if (host->flags & SDHCI_DEVICE_DEAD) { 1421 spin_unlock_irqrestore(&host->lock, flags); 1422 if (host->vmmc && ios->power_mode == MMC_POWER_OFF) 1423 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0); 1424 return; 1425 } 1426 1427 /* 1428 * Reset the chip on each power off. 1429 * Should clear out any weird states. 1430 */ 1431 if (ios->power_mode == MMC_POWER_OFF) { 1432 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1433 sdhci_reinit(host); 1434 } 1435 1436 if (host->version >= SDHCI_SPEC_300 && 1437 (ios->power_mode == MMC_POWER_UP) && 1438 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1439 sdhci_enable_preset_value(host, false); 1440 1441 if (!ios->clock || ios->clock != host->clock) { 1442 sdhci_set_clock(host, ios->clock); 1443 host->clock = ios->clock; 1444 } 1445 1446 if (ios->power_mode == MMC_POWER_OFF) 1447 vdd_bit = sdhci_set_power(host, -1); 1448 else 1449 vdd_bit = sdhci_set_power(host, ios->vdd); 1450 1451 if (host->vmmc && vdd_bit != -1) { 1452 spin_unlock_irqrestore(&host->lock, flags); 1453 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit); 1454 spin_lock_irqsave(&host->lock, flags); 1455 } 1456 1457 if (host->ops->platform_send_init_74_clocks) 1458 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1459 1460 host->ops->set_bus_width(host, ios->bus_width); 1461 1462 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1463 1464 if ((ios->timing == MMC_TIMING_SD_HS || 1465 ios->timing == MMC_TIMING_MMC_HS) 1466 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1467 ctrl |= SDHCI_CTRL_HISPD; 1468 else 1469 ctrl &= ~SDHCI_CTRL_HISPD; 1470 1471 if (host->version >= SDHCI_SPEC_300) { 1472 u16 clk, ctrl_2; 1473 1474 /* In case of UHS-I modes, set High Speed Enable */ 1475 if ((ios->timing == MMC_TIMING_MMC_HS200) || 1476 (ios->timing == MMC_TIMING_MMC_DDR52) || 1477 (ios->timing == MMC_TIMING_UHS_SDR50) || 1478 (ios->timing == MMC_TIMING_UHS_SDR104) || 1479 (ios->timing == MMC_TIMING_UHS_DDR50) || 1480 (ios->timing == MMC_TIMING_UHS_SDR25)) 1481 ctrl |= SDHCI_CTRL_HISPD; 1482 1483 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1484 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1485 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1486 /* 1487 * We only need to set Driver Strength if the 1488 * preset value enable is not set. 1489 */ 1490 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1491 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1492 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1493 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1494 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1495 1496 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1497 } else { 1498 /* 1499 * According to SDHC Spec v3.00, if the Preset Value 1500 * Enable in the Host Control 2 register is set, we 1501 * need to reset SD Clock Enable before changing High 1502 * Speed Enable to avoid generating clock gliches. 1503 */ 1504 1505 /* Reset SD Clock Enable */ 1506 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1507 clk &= ~SDHCI_CLOCK_CARD_EN; 1508 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1509 1510 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1511 1512 /* Re-enable SD Clock */ 1513 sdhci_set_clock(host, host->clock); 1514 } 1515 1516 1517 /* Reset SD Clock Enable */ 1518 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1519 clk &= ~SDHCI_CLOCK_CARD_EN; 1520 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1521 1522 if (host->ops->set_uhs_signaling) 1523 host->ops->set_uhs_signaling(host, ios->timing); 1524 else { 1525 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1526 /* Select Bus Speed Mode for host */ 1527 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1528 if ((ios->timing == MMC_TIMING_MMC_HS200) || 1529 (ios->timing == MMC_TIMING_UHS_SDR104)) 1530 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1531 else if (ios->timing == MMC_TIMING_UHS_SDR12) 1532 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1533 else if (ios->timing == MMC_TIMING_UHS_SDR25) 1534 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1535 else if (ios->timing == MMC_TIMING_UHS_SDR50) 1536 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1537 else if ((ios->timing == MMC_TIMING_UHS_DDR50) || 1538 (ios->timing == MMC_TIMING_MMC_DDR52)) 1539 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1540 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1541 } 1542 1543 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1544 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1545 (ios->timing == MMC_TIMING_UHS_SDR25) || 1546 (ios->timing == MMC_TIMING_UHS_SDR50) || 1547 (ios->timing == MMC_TIMING_UHS_SDR104) || 1548 (ios->timing == MMC_TIMING_UHS_DDR50))) { 1549 u16 preset; 1550 1551 sdhci_enable_preset_value(host, true); 1552 preset = sdhci_get_preset_value(host); 1553 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 1554 >> SDHCI_PRESET_DRV_SHIFT; 1555 } 1556 1557 /* Re-enable SD Clock */ 1558 sdhci_set_clock(host, host->clock); 1559 } else 1560 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1561 1562 /* 1563 * Some (ENE) controllers go apeshit on some ios operation, 1564 * signalling timeout and CRC errors even on CMD0. Resetting 1565 * it on each ios seems to solve the problem. 1566 */ 1567 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1568 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1569 1570 mmiowb(); 1571 spin_unlock_irqrestore(&host->lock, flags); 1572 } 1573 1574 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1575 { 1576 struct sdhci_host *host = mmc_priv(mmc); 1577 1578 sdhci_runtime_pm_get(host); 1579 sdhci_do_set_ios(host, ios); 1580 sdhci_runtime_pm_put(host); 1581 } 1582 1583 static int sdhci_do_get_cd(struct sdhci_host *host) 1584 { 1585 int gpio_cd = mmc_gpio_get_cd(host->mmc); 1586 1587 if (host->flags & SDHCI_DEVICE_DEAD) 1588 return 0; 1589 1590 /* If polling/nonremovable, assume that the card is always present. */ 1591 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 1592 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 1593 return 1; 1594 1595 /* Try slot gpio detect */ 1596 if (!IS_ERR_VALUE(gpio_cd)) 1597 return !!gpio_cd; 1598 1599 /* Host native card detect */ 1600 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1601 } 1602 1603 static int sdhci_get_cd(struct mmc_host *mmc) 1604 { 1605 struct sdhci_host *host = mmc_priv(mmc); 1606 int ret; 1607 1608 sdhci_runtime_pm_get(host); 1609 ret = sdhci_do_get_cd(host); 1610 sdhci_runtime_pm_put(host); 1611 return ret; 1612 } 1613 1614 static int sdhci_check_ro(struct sdhci_host *host) 1615 { 1616 unsigned long flags; 1617 int is_readonly; 1618 1619 spin_lock_irqsave(&host->lock, flags); 1620 1621 if (host->flags & SDHCI_DEVICE_DEAD) 1622 is_readonly = 0; 1623 else if (host->ops->get_ro) 1624 is_readonly = host->ops->get_ro(host); 1625 else 1626 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1627 & SDHCI_WRITE_PROTECT); 1628 1629 spin_unlock_irqrestore(&host->lock, flags); 1630 1631 /* This quirk needs to be replaced by a callback-function later */ 1632 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1633 !is_readonly : is_readonly; 1634 } 1635 1636 #define SAMPLE_COUNT 5 1637 1638 static int sdhci_do_get_ro(struct sdhci_host *host) 1639 { 1640 int i, ro_count; 1641 1642 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1643 return sdhci_check_ro(host); 1644 1645 ro_count = 0; 1646 for (i = 0; i < SAMPLE_COUNT; i++) { 1647 if (sdhci_check_ro(host)) { 1648 if (++ro_count > SAMPLE_COUNT / 2) 1649 return 1; 1650 } 1651 msleep(30); 1652 } 1653 return 0; 1654 } 1655 1656 static void sdhci_hw_reset(struct mmc_host *mmc) 1657 { 1658 struct sdhci_host *host = mmc_priv(mmc); 1659 1660 if (host->ops && host->ops->hw_reset) 1661 host->ops->hw_reset(host); 1662 } 1663 1664 static int sdhci_get_ro(struct mmc_host *mmc) 1665 { 1666 struct sdhci_host *host = mmc_priv(mmc); 1667 int ret; 1668 1669 sdhci_runtime_pm_get(host); 1670 ret = sdhci_do_get_ro(host); 1671 sdhci_runtime_pm_put(host); 1672 return ret; 1673 } 1674 1675 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1676 { 1677 if (!(host->flags & SDHCI_DEVICE_DEAD)) { 1678 if (enable) 1679 host->ier |= SDHCI_INT_CARD_INT; 1680 else 1681 host->ier &= ~SDHCI_INT_CARD_INT; 1682 1683 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1684 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1685 mmiowb(); 1686 } 1687 } 1688 1689 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1690 { 1691 struct sdhci_host *host = mmc_priv(mmc); 1692 unsigned long flags; 1693 1694 sdhci_runtime_pm_get(host); 1695 1696 spin_lock_irqsave(&host->lock, flags); 1697 if (enable) 1698 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1699 else 1700 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1701 1702 sdhci_enable_sdio_irq_nolock(host, enable); 1703 spin_unlock_irqrestore(&host->lock, flags); 1704 1705 sdhci_runtime_pm_put(host); 1706 } 1707 1708 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 1709 struct mmc_ios *ios) 1710 { 1711 u16 ctrl; 1712 int ret; 1713 1714 /* 1715 * Signal Voltage Switching is only applicable for Host Controllers 1716 * v3.00 and above. 1717 */ 1718 if (host->version < SDHCI_SPEC_300) 1719 return 0; 1720 1721 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1722 1723 switch (ios->signal_voltage) { 1724 case MMC_SIGNAL_VOLTAGE_330: 1725 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1726 ctrl &= ~SDHCI_CTRL_VDD_180; 1727 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1728 1729 if (host->vqmmc) { 1730 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000); 1731 if (ret) { 1732 pr_warning("%s: Switching to 3.3V signalling voltage " 1733 " failed\n", mmc_hostname(host->mmc)); 1734 return -EIO; 1735 } 1736 } 1737 /* Wait for 5ms */ 1738 usleep_range(5000, 5500); 1739 1740 /* 3.3V regulator output should be stable within 5 ms */ 1741 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1742 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1743 return 0; 1744 1745 pr_warning("%s: 3.3V regulator output did not became stable\n", 1746 mmc_hostname(host->mmc)); 1747 1748 return -EAGAIN; 1749 case MMC_SIGNAL_VOLTAGE_180: 1750 if (host->vqmmc) { 1751 ret = regulator_set_voltage(host->vqmmc, 1752 1700000, 1950000); 1753 if (ret) { 1754 pr_warning("%s: Switching to 1.8V signalling voltage " 1755 " failed\n", mmc_hostname(host->mmc)); 1756 return -EIO; 1757 } 1758 } 1759 1760 /* 1761 * Enable 1.8V Signal Enable in the Host Control2 1762 * register 1763 */ 1764 ctrl |= SDHCI_CTRL_VDD_180; 1765 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1766 1767 /* Wait for 5ms */ 1768 usleep_range(5000, 5500); 1769 1770 /* 1.8V regulator output should be stable within 5 ms */ 1771 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1772 if (ctrl & SDHCI_CTRL_VDD_180) 1773 return 0; 1774 1775 pr_warning("%s: 1.8V regulator output did not became stable\n", 1776 mmc_hostname(host->mmc)); 1777 1778 return -EAGAIN; 1779 case MMC_SIGNAL_VOLTAGE_120: 1780 if (host->vqmmc) { 1781 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000); 1782 if (ret) { 1783 pr_warning("%s: Switching to 1.2V signalling voltage " 1784 " failed\n", mmc_hostname(host->mmc)); 1785 return -EIO; 1786 } 1787 } 1788 return 0; 1789 default: 1790 /* No signal voltage switch required */ 1791 return 0; 1792 } 1793 } 1794 1795 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1796 struct mmc_ios *ios) 1797 { 1798 struct sdhci_host *host = mmc_priv(mmc); 1799 int err; 1800 1801 if (host->version < SDHCI_SPEC_300) 1802 return 0; 1803 sdhci_runtime_pm_get(host); 1804 err = sdhci_do_start_signal_voltage_switch(host, ios); 1805 sdhci_runtime_pm_put(host); 1806 return err; 1807 } 1808 1809 static int sdhci_card_busy(struct mmc_host *mmc) 1810 { 1811 struct sdhci_host *host = mmc_priv(mmc); 1812 u32 present_state; 1813 1814 sdhci_runtime_pm_get(host); 1815 /* Check whether DAT[3:0] is 0000 */ 1816 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1817 sdhci_runtime_pm_put(host); 1818 1819 return !(present_state & SDHCI_DATA_LVL_MASK); 1820 } 1821 1822 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1823 { 1824 struct sdhci_host *host; 1825 u16 ctrl; 1826 int tuning_loop_counter = MAX_TUNING_LOOP; 1827 unsigned long timeout; 1828 int err = 0; 1829 bool requires_tuning_nonuhs = false; 1830 unsigned long flags; 1831 1832 host = mmc_priv(mmc); 1833 1834 sdhci_runtime_pm_get(host); 1835 spin_lock_irqsave(&host->lock, flags); 1836 1837 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1838 1839 /* 1840 * The Host Controller needs tuning only in case of SDR104 mode 1841 * and for SDR50 mode when Use Tuning for SDR50 is set in the 1842 * Capabilities register. 1843 * If the Host Controller supports the HS200 mode then the 1844 * tuning function has to be executed. 1845 */ 1846 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && 1847 (host->flags & SDHCI_SDR50_NEEDS_TUNING || 1848 host->flags & SDHCI_SDR104_NEEDS_TUNING)) 1849 requires_tuning_nonuhs = true; 1850 1851 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || 1852 requires_tuning_nonuhs) 1853 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1854 else { 1855 spin_unlock_irqrestore(&host->lock, flags); 1856 sdhci_runtime_pm_put(host); 1857 return 0; 1858 } 1859 1860 if (host->ops->platform_execute_tuning) { 1861 spin_unlock_irqrestore(&host->lock, flags); 1862 err = host->ops->platform_execute_tuning(host, opcode); 1863 sdhci_runtime_pm_put(host); 1864 return err; 1865 } 1866 1867 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1868 1869 /* 1870 * As per the Host Controller spec v3.00, tuning command 1871 * generates Buffer Read Ready interrupt, so enable that. 1872 * 1873 * Note: The spec clearly says that when tuning sequence 1874 * is being performed, the controller does not generate 1875 * interrupts other than Buffer Read Ready interrupt. But 1876 * to make sure we don't hit a controller bug, we _only_ 1877 * enable Buffer Read Ready interrupt here. 1878 */ 1879 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 1880 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 1881 1882 /* 1883 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1884 * of loops reaches 40 times or a timeout of 150ms occurs. 1885 */ 1886 timeout = 150; 1887 do { 1888 struct mmc_command cmd = {0}; 1889 struct mmc_request mrq = {NULL}; 1890 1891 if (!tuning_loop_counter && !timeout) 1892 break; 1893 1894 cmd.opcode = opcode; 1895 cmd.arg = 0; 1896 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1897 cmd.retries = 0; 1898 cmd.data = NULL; 1899 cmd.error = 0; 1900 1901 mrq.cmd = &cmd; 1902 host->mrq = &mrq; 1903 1904 /* 1905 * In response to CMD19, the card sends 64 bytes of tuning 1906 * block to the Host Controller. So we set the block size 1907 * to 64 here. 1908 */ 1909 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1910 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1911 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1912 SDHCI_BLOCK_SIZE); 1913 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1914 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1915 SDHCI_BLOCK_SIZE); 1916 } else { 1917 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1918 SDHCI_BLOCK_SIZE); 1919 } 1920 1921 /* 1922 * The tuning block is sent by the card to the host controller. 1923 * So we set the TRNS_READ bit in the Transfer Mode register. 1924 * This also takes care of setting DMA Enable and Multi Block 1925 * Select in the same register to 0. 1926 */ 1927 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1928 1929 sdhci_send_command(host, &cmd); 1930 1931 host->cmd = NULL; 1932 host->mrq = NULL; 1933 1934 spin_unlock_irqrestore(&host->lock, flags); 1935 /* Wait for Buffer Read Ready interrupt */ 1936 wait_event_interruptible_timeout(host->buf_ready_int, 1937 (host->tuning_done == 1), 1938 msecs_to_jiffies(50)); 1939 spin_lock_irqsave(&host->lock, flags); 1940 1941 if (!host->tuning_done) { 1942 pr_info(DRIVER_NAME ": Timeout waiting for " 1943 "Buffer Read Ready interrupt during tuning " 1944 "procedure, falling back to fixed sampling " 1945 "clock\n"); 1946 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1947 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1948 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1949 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1950 1951 err = -EIO; 1952 goto out; 1953 } 1954 1955 host->tuning_done = 0; 1956 1957 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1958 tuning_loop_counter--; 1959 timeout--; 1960 1961 /* eMMC spec does not require a delay between tuning cycles */ 1962 if (opcode == MMC_SEND_TUNING_BLOCK) 1963 mdelay(1); 1964 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1965 1966 /* 1967 * The Host Driver has exhausted the maximum number of loops allowed, 1968 * so use fixed sampling frequency. 1969 */ 1970 if (!tuning_loop_counter || !timeout) { 1971 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1972 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1973 err = -EIO; 1974 } else { 1975 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1976 pr_info(DRIVER_NAME ": Tuning procedure" 1977 " failed, falling back to fixed sampling" 1978 " clock\n"); 1979 err = -EIO; 1980 } 1981 } 1982 1983 out: 1984 /* 1985 * If this is the very first time we are here, we start the retuning 1986 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 1987 * flag won't be set, we check this condition before actually starting 1988 * the timer. 1989 */ 1990 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 1991 (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 1992 host->flags |= SDHCI_USING_RETUNING_TIMER; 1993 mod_timer(&host->tuning_timer, jiffies + 1994 host->tuning_count * HZ); 1995 /* Tuning mode 1 limits the maximum data length to 4MB */ 1996 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 1997 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) { 1998 host->flags &= ~SDHCI_NEEDS_RETUNING; 1999 /* Reload the new initial value for timer */ 2000 mod_timer(&host->tuning_timer, jiffies + 2001 host->tuning_count * HZ); 2002 } 2003 2004 /* 2005 * In case tuning fails, host controllers which support re-tuning can 2006 * try tuning again at a later time, when the re-tuning timer expires. 2007 * So for these controllers, we return 0. Since there might be other 2008 * controllers who do not have this capability, we return error for 2009 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using 2010 * a retuning timer to do the retuning for the card. 2011 */ 2012 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) 2013 err = 0; 2014 2015 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2016 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2017 spin_unlock_irqrestore(&host->lock, flags); 2018 sdhci_runtime_pm_put(host); 2019 2020 return err; 2021 } 2022 2023 2024 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2025 { 2026 u16 ctrl; 2027 2028 /* Host Controller v3.00 defines preset value registers */ 2029 if (host->version < SDHCI_SPEC_300) 2030 return; 2031 2032 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2033 2034 /* 2035 * We only enable or disable Preset Value if they are not already 2036 * enabled or disabled respectively. Otherwise, we bail out. 2037 */ 2038 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 2039 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2040 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2041 host->flags |= SDHCI_PV_ENABLED; 2042 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 2043 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2044 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2045 host->flags &= ~SDHCI_PV_ENABLED; 2046 } 2047 } 2048 2049 static void sdhci_card_event(struct mmc_host *mmc) 2050 { 2051 struct sdhci_host *host = mmc_priv(mmc); 2052 unsigned long flags; 2053 2054 /* First check if client has provided their own card event */ 2055 if (host->ops->card_event) 2056 host->ops->card_event(host); 2057 2058 spin_lock_irqsave(&host->lock, flags); 2059 2060 /* Check host->mrq first in case we are runtime suspended */ 2061 if (host->mrq && !sdhci_do_get_cd(host)) { 2062 pr_err("%s: Card removed during transfer!\n", 2063 mmc_hostname(host->mmc)); 2064 pr_err("%s: Resetting controller.\n", 2065 mmc_hostname(host->mmc)); 2066 2067 sdhci_do_reset(host, SDHCI_RESET_CMD); 2068 sdhci_do_reset(host, SDHCI_RESET_DATA); 2069 2070 host->mrq->cmd->error = -ENOMEDIUM; 2071 tasklet_schedule(&host->finish_tasklet); 2072 } 2073 2074 spin_unlock_irqrestore(&host->lock, flags); 2075 } 2076 2077 static const struct mmc_host_ops sdhci_ops = { 2078 .request = sdhci_request, 2079 .set_ios = sdhci_set_ios, 2080 .get_cd = sdhci_get_cd, 2081 .get_ro = sdhci_get_ro, 2082 .hw_reset = sdhci_hw_reset, 2083 .enable_sdio_irq = sdhci_enable_sdio_irq, 2084 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2085 .execute_tuning = sdhci_execute_tuning, 2086 .card_event = sdhci_card_event, 2087 .card_busy = sdhci_card_busy, 2088 }; 2089 2090 /*****************************************************************************\ 2091 * * 2092 * Tasklets * 2093 * * 2094 \*****************************************************************************/ 2095 2096 static void sdhci_tasklet_finish(unsigned long param) 2097 { 2098 struct sdhci_host *host; 2099 unsigned long flags; 2100 struct mmc_request *mrq; 2101 2102 host = (struct sdhci_host*)param; 2103 2104 spin_lock_irqsave(&host->lock, flags); 2105 2106 /* 2107 * If this tasklet gets rescheduled while running, it will 2108 * be run again afterwards but without any active request. 2109 */ 2110 if (!host->mrq) { 2111 spin_unlock_irqrestore(&host->lock, flags); 2112 return; 2113 } 2114 2115 del_timer(&host->timer); 2116 2117 mrq = host->mrq; 2118 2119 /* 2120 * The controller needs a reset of internal state machines 2121 * upon error conditions. 2122 */ 2123 if (!(host->flags & SDHCI_DEVICE_DEAD) && 2124 ((mrq->cmd && mrq->cmd->error) || 2125 (mrq->data && (mrq->data->error || 2126 (mrq->data->stop && mrq->data->stop->error))) || 2127 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2128 2129 /* Some controllers need this kick or reset won't work here */ 2130 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2131 /* This is to force an update */ 2132 sdhci_set_clock(host, host->clock); 2133 2134 /* Spec says we should do both at the same time, but Ricoh 2135 controllers do not like that. */ 2136 sdhci_do_reset(host, SDHCI_RESET_CMD); 2137 sdhci_do_reset(host, SDHCI_RESET_DATA); 2138 } 2139 2140 host->mrq = NULL; 2141 host->cmd = NULL; 2142 host->data = NULL; 2143 2144 #ifndef SDHCI_USE_LEDS_CLASS 2145 sdhci_deactivate_led(host); 2146 #endif 2147 2148 mmiowb(); 2149 spin_unlock_irqrestore(&host->lock, flags); 2150 2151 mmc_request_done(host->mmc, mrq); 2152 sdhci_runtime_pm_put(host); 2153 } 2154 2155 static void sdhci_timeout_timer(unsigned long data) 2156 { 2157 struct sdhci_host *host; 2158 unsigned long flags; 2159 2160 host = (struct sdhci_host*)data; 2161 2162 spin_lock_irqsave(&host->lock, flags); 2163 2164 if (host->mrq) { 2165 pr_err("%s: Timeout waiting for hardware " 2166 "interrupt.\n", mmc_hostname(host->mmc)); 2167 sdhci_dumpregs(host); 2168 2169 if (host->data) { 2170 host->data->error = -ETIMEDOUT; 2171 sdhci_finish_data(host); 2172 } else { 2173 if (host->cmd) 2174 host->cmd->error = -ETIMEDOUT; 2175 else 2176 host->mrq->cmd->error = -ETIMEDOUT; 2177 2178 tasklet_schedule(&host->finish_tasklet); 2179 } 2180 } 2181 2182 mmiowb(); 2183 spin_unlock_irqrestore(&host->lock, flags); 2184 } 2185 2186 static void sdhci_tuning_timer(unsigned long data) 2187 { 2188 struct sdhci_host *host; 2189 unsigned long flags; 2190 2191 host = (struct sdhci_host *)data; 2192 2193 spin_lock_irqsave(&host->lock, flags); 2194 2195 host->flags |= SDHCI_NEEDS_RETUNING; 2196 2197 spin_unlock_irqrestore(&host->lock, flags); 2198 } 2199 2200 /*****************************************************************************\ 2201 * * 2202 * Interrupt handling * 2203 * * 2204 \*****************************************************************************/ 2205 2206 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 2207 { 2208 BUG_ON(intmask == 0); 2209 2210 if (!host->cmd) { 2211 pr_err("%s: Got command interrupt 0x%08x even " 2212 "though no command operation was in progress.\n", 2213 mmc_hostname(host->mmc), (unsigned)intmask); 2214 sdhci_dumpregs(host); 2215 return; 2216 } 2217 2218 if (intmask & SDHCI_INT_TIMEOUT) 2219 host->cmd->error = -ETIMEDOUT; 2220 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 2221 SDHCI_INT_INDEX)) 2222 host->cmd->error = -EILSEQ; 2223 2224 if (host->cmd->error) { 2225 tasklet_schedule(&host->finish_tasklet); 2226 return; 2227 } 2228 2229 /* 2230 * The host can send and interrupt when the busy state has 2231 * ended, allowing us to wait without wasting CPU cycles. 2232 * Unfortunately this is overloaded on the "data complete" 2233 * interrupt, so we need to take some care when handling 2234 * it. 2235 * 2236 * Note: The 1.0 specification is a bit ambiguous about this 2237 * feature so there might be some problems with older 2238 * controllers. 2239 */ 2240 if (host->cmd->flags & MMC_RSP_BUSY) { 2241 if (host->cmd->data) 2242 DBG("Cannot wait for busy signal when also " 2243 "doing a data transfer"); 2244 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) 2245 return; 2246 2247 /* The controller does not support the end-of-busy IRQ, 2248 * fall through and take the SDHCI_INT_RESPONSE */ 2249 } 2250 2251 if (intmask & SDHCI_INT_RESPONSE) 2252 sdhci_finish_command(host); 2253 } 2254 2255 #ifdef CONFIG_MMC_DEBUG 2256 static void sdhci_show_adma_error(struct sdhci_host *host) 2257 { 2258 const char *name = mmc_hostname(host->mmc); 2259 u8 *desc = host->adma_desc; 2260 __le32 *dma; 2261 __le16 *len; 2262 u8 attr; 2263 2264 sdhci_dumpregs(host); 2265 2266 while (true) { 2267 dma = (__le32 *)(desc + 4); 2268 len = (__le16 *)(desc + 2); 2269 attr = *desc; 2270 2271 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2272 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 2273 2274 desc += 8; 2275 2276 if (attr & 2) 2277 break; 2278 } 2279 } 2280 #else 2281 static void sdhci_show_adma_error(struct sdhci_host *host) { } 2282 #endif 2283 2284 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2285 { 2286 u32 command; 2287 BUG_ON(intmask == 0); 2288 2289 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2290 if (intmask & SDHCI_INT_DATA_AVAIL) { 2291 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2292 if (command == MMC_SEND_TUNING_BLOCK || 2293 command == MMC_SEND_TUNING_BLOCK_HS200) { 2294 host->tuning_done = 1; 2295 wake_up(&host->buf_ready_int); 2296 return; 2297 } 2298 } 2299 2300 if (!host->data) { 2301 /* 2302 * The "data complete" interrupt is also used to 2303 * indicate that a busy state has ended. See comment 2304 * above in sdhci_cmd_irq(). 2305 */ 2306 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2307 if (intmask & SDHCI_INT_DATA_END) { 2308 sdhci_finish_command(host); 2309 return; 2310 } 2311 } 2312 2313 pr_err("%s: Got data interrupt 0x%08x even " 2314 "though no data operation was in progress.\n", 2315 mmc_hostname(host->mmc), (unsigned)intmask); 2316 sdhci_dumpregs(host); 2317 2318 return; 2319 } 2320 2321 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2322 host->data->error = -ETIMEDOUT; 2323 else if (intmask & SDHCI_INT_DATA_END_BIT) 2324 host->data->error = -EILSEQ; 2325 else if ((intmask & SDHCI_INT_DATA_CRC) && 2326 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2327 != MMC_BUS_TEST_R) 2328 host->data->error = -EILSEQ; 2329 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2330 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2331 sdhci_show_adma_error(host); 2332 host->data->error = -EIO; 2333 if (host->ops->adma_workaround) 2334 host->ops->adma_workaround(host, intmask); 2335 } 2336 2337 if (host->data->error) 2338 sdhci_finish_data(host); 2339 else { 2340 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2341 sdhci_transfer_pio(host); 2342 2343 /* 2344 * We currently don't do anything fancy with DMA 2345 * boundaries, but as we can't disable the feature 2346 * we need to at least restart the transfer. 2347 * 2348 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2349 * should return a valid address to continue from, but as 2350 * some controllers are faulty, don't trust them. 2351 */ 2352 if (intmask & SDHCI_INT_DMA_END) { 2353 u32 dmastart, dmanow; 2354 dmastart = sg_dma_address(host->data->sg); 2355 dmanow = dmastart + host->data->bytes_xfered; 2356 /* 2357 * Force update to the next DMA block boundary. 2358 */ 2359 dmanow = (dmanow & 2360 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2361 SDHCI_DEFAULT_BOUNDARY_SIZE; 2362 host->data->bytes_xfered = dmanow - dmastart; 2363 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2364 " next 0x%08x\n", 2365 mmc_hostname(host->mmc), dmastart, 2366 host->data->bytes_xfered, dmanow); 2367 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2368 } 2369 2370 if (intmask & SDHCI_INT_DATA_END) { 2371 if (host->cmd) { 2372 /* 2373 * Data managed to finish before the 2374 * command completed. Make sure we do 2375 * things in the proper order. 2376 */ 2377 host->data_early = 1; 2378 } else { 2379 sdhci_finish_data(host); 2380 } 2381 } 2382 } 2383 } 2384 2385 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2386 { 2387 irqreturn_t result = IRQ_NONE; 2388 struct sdhci_host *host = dev_id; 2389 u32 intmask, mask, unexpected = 0; 2390 int max_loops = 16; 2391 2392 spin_lock(&host->lock); 2393 2394 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 2395 spin_unlock(&host->lock); 2396 return IRQ_NONE; 2397 } 2398 2399 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2400 if (!intmask || intmask == 0xffffffff) { 2401 result = IRQ_NONE; 2402 goto out; 2403 } 2404 2405 do { 2406 /* Clear selected interrupts. */ 2407 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2408 SDHCI_INT_BUS_POWER); 2409 sdhci_writel(host, mask, SDHCI_INT_STATUS); 2410 2411 DBG("*** %s got interrupt: 0x%08x\n", 2412 mmc_hostname(host->mmc), intmask); 2413 2414 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2415 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2416 SDHCI_CARD_PRESENT; 2417 2418 /* 2419 * There is a observation on i.mx esdhc. INSERT 2420 * bit will be immediately set again when it gets 2421 * cleared, if a card is inserted. We have to mask 2422 * the irq to prevent interrupt storm which will 2423 * freeze the system. And the REMOVE gets the 2424 * same situation. 2425 * 2426 * More testing are needed here to ensure it works 2427 * for other platforms though. 2428 */ 2429 host->ier &= ~(SDHCI_INT_CARD_INSERT | 2430 SDHCI_INT_CARD_REMOVE); 2431 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2432 SDHCI_INT_CARD_INSERT; 2433 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2434 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2435 2436 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2437 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2438 2439 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 2440 SDHCI_INT_CARD_REMOVE); 2441 result = IRQ_WAKE_THREAD; 2442 } 2443 2444 if (intmask & SDHCI_INT_CMD_MASK) 2445 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 2446 2447 if (intmask & SDHCI_INT_DATA_MASK) 2448 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2449 2450 if (intmask & SDHCI_INT_BUS_POWER) 2451 pr_err("%s: Card is consuming too much power!\n", 2452 mmc_hostname(host->mmc)); 2453 2454 if (intmask & SDHCI_INT_CARD_INT) { 2455 sdhci_enable_sdio_irq_nolock(host, false); 2456 host->thread_isr |= SDHCI_INT_CARD_INT; 2457 result = IRQ_WAKE_THREAD; 2458 } 2459 2460 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2461 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2462 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 2463 SDHCI_INT_CARD_INT); 2464 2465 if (intmask) { 2466 unexpected |= intmask; 2467 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2468 } 2469 2470 if (result == IRQ_NONE) 2471 result = IRQ_HANDLED; 2472 2473 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2474 } while (intmask && --max_loops); 2475 out: 2476 spin_unlock(&host->lock); 2477 2478 if (unexpected) { 2479 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2480 mmc_hostname(host->mmc), unexpected); 2481 sdhci_dumpregs(host); 2482 } 2483 2484 return result; 2485 } 2486 2487 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2488 { 2489 struct sdhci_host *host = dev_id; 2490 unsigned long flags; 2491 u32 isr; 2492 2493 spin_lock_irqsave(&host->lock, flags); 2494 isr = host->thread_isr; 2495 host->thread_isr = 0; 2496 spin_unlock_irqrestore(&host->lock, flags); 2497 2498 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2499 sdhci_card_event(host->mmc); 2500 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 2501 } 2502 2503 if (isr & SDHCI_INT_CARD_INT) { 2504 sdio_run_irqs(host->mmc); 2505 2506 spin_lock_irqsave(&host->lock, flags); 2507 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2508 sdhci_enable_sdio_irq_nolock(host, true); 2509 spin_unlock_irqrestore(&host->lock, flags); 2510 } 2511 2512 return isr ? IRQ_HANDLED : IRQ_NONE; 2513 } 2514 2515 /*****************************************************************************\ 2516 * * 2517 * Suspend/resume * 2518 * * 2519 \*****************************************************************************/ 2520 2521 #ifdef CONFIG_PM 2522 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2523 { 2524 u8 val; 2525 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2526 | SDHCI_WAKE_ON_INT; 2527 2528 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2529 val |= mask ; 2530 /* Avoid fake wake up */ 2531 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2532 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2533 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2534 } 2535 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2536 2537 void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2538 { 2539 u8 val; 2540 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2541 | SDHCI_WAKE_ON_INT; 2542 2543 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2544 val &= ~mask; 2545 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2546 } 2547 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups); 2548 2549 int sdhci_suspend_host(struct sdhci_host *host) 2550 { 2551 if (host->ops->platform_suspend) 2552 host->ops->platform_suspend(host); 2553 2554 sdhci_disable_card_detection(host); 2555 2556 /* Disable tuning since we are suspending */ 2557 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2558 del_timer_sync(&host->tuning_timer); 2559 host->flags &= ~SDHCI_NEEDS_RETUNING; 2560 } 2561 2562 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2563 host->ier = 0; 2564 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2565 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2566 free_irq(host->irq, host); 2567 } else { 2568 sdhci_enable_irq_wakeups(host); 2569 enable_irq_wake(host->irq); 2570 } 2571 return 0; 2572 } 2573 2574 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2575 2576 int sdhci_resume_host(struct sdhci_host *host) 2577 { 2578 int ret = 0; 2579 2580 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2581 if (host->ops->enable_dma) 2582 host->ops->enable_dma(host); 2583 } 2584 2585 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2586 ret = request_threaded_irq(host->irq, sdhci_irq, 2587 sdhci_thread_irq, IRQF_SHARED, 2588 mmc_hostname(host->mmc), host); 2589 if (ret) 2590 return ret; 2591 } else { 2592 sdhci_disable_irq_wakeups(host); 2593 disable_irq_wake(host->irq); 2594 } 2595 2596 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2597 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2598 /* Card keeps power but host controller does not */ 2599 sdhci_init(host, 0); 2600 host->pwr = 0; 2601 host->clock = 0; 2602 sdhci_do_set_ios(host, &host->mmc->ios); 2603 } else { 2604 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2605 mmiowb(); 2606 } 2607 2608 sdhci_enable_card_detection(host); 2609 2610 if (host->ops->platform_resume) 2611 host->ops->platform_resume(host); 2612 2613 /* Set the re-tuning expiration flag */ 2614 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2615 host->flags |= SDHCI_NEEDS_RETUNING; 2616 2617 return ret; 2618 } 2619 2620 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2621 #endif /* CONFIG_PM */ 2622 2623 #ifdef CONFIG_PM_RUNTIME 2624 2625 static int sdhci_runtime_pm_get(struct sdhci_host *host) 2626 { 2627 return pm_runtime_get_sync(host->mmc->parent); 2628 } 2629 2630 static int sdhci_runtime_pm_put(struct sdhci_host *host) 2631 { 2632 pm_runtime_mark_last_busy(host->mmc->parent); 2633 return pm_runtime_put_autosuspend(host->mmc->parent); 2634 } 2635 2636 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 2637 { 2638 if (host->runtime_suspended || host->bus_on) 2639 return; 2640 host->bus_on = true; 2641 pm_runtime_get_noresume(host->mmc->parent); 2642 } 2643 2644 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 2645 { 2646 if (host->runtime_suspended || !host->bus_on) 2647 return; 2648 host->bus_on = false; 2649 pm_runtime_put_noidle(host->mmc->parent); 2650 } 2651 2652 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2653 { 2654 unsigned long flags; 2655 int ret = 0; 2656 2657 /* Disable tuning since we are suspending */ 2658 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2659 del_timer_sync(&host->tuning_timer); 2660 host->flags &= ~SDHCI_NEEDS_RETUNING; 2661 } 2662 2663 spin_lock_irqsave(&host->lock, flags); 2664 host->ier &= SDHCI_INT_CARD_INT; 2665 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2666 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2667 spin_unlock_irqrestore(&host->lock, flags); 2668 2669 synchronize_hardirq(host->irq); 2670 2671 spin_lock_irqsave(&host->lock, flags); 2672 host->runtime_suspended = true; 2673 spin_unlock_irqrestore(&host->lock, flags); 2674 2675 return ret; 2676 } 2677 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2678 2679 int sdhci_runtime_resume_host(struct sdhci_host *host) 2680 { 2681 unsigned long flags; 2682 int ret = 0, host_flags = host->flags; 2683 2684 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2685 if (host->ops->enable_dma) 2686 host->ops->enable_dma(host); 2687 } 2688 2689 sdhci_init(host, 0); 2690 2691 /* Force clock and power re-program */ 2692 host->pwr = 0; 2693 host->clock = 0; 2694 sdhci_do_set_ios(host, &host->mmc->ios); 2695 2696 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 2697 if ((host_flags & SDHCI_PV_ENABLED) && 2698 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2699 spin_lock_irqsave(&host->lock, flags); 2700 sdhci_enable_preset_value(host, true); 2701 spin_unlock_irqrestore(&host->lock, flags); 2702 } 2703 2704 /* Set the re-tuning expiration flag */ 2705 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2706 host->flags |= SDHCI_NEEDS_RETUNING; 2707 2708 spin_lock_irqsave(&host->lock, flags); 2709 2710 host->runtime_suspended = false; 2711 2712 /* Enable SDIO IRQ */ 2713 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2714 sdhci_enable_sdio_irq_nolock(host, true); 2715 2716 /* Enable Card Detection */ 2717 sdhci_enable_card_detection(host); 2718 2719 spin_unlock_irqrestore(&host->lock, flags); 2720 2721 return ret; 2722 } 2723 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2724 2725 #endif 2726 2727 /*****************************************************************************\ 2728 * * 2729 * Device allocation/registration * 2730 * * 2731 \*****************************************************************************/ 2732 2733 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2734 size_t priv_size) 2735 { 2736 struct mmc_host *mmc; 2737 struct sdhci_host *host; 2738 2739 WARN_ON(dev == NULL); 2740 2741 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2742 if (!mmc) 2743 return ERR_PTR(-ENOMEM); 2744 2745 host = mmc_priv(mmc); 2746 host->mmc = mmc; 2747 2748 return host; 2749 } 2750 2751 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2752 2753 int sdhci_add_host(struct sdhci_host *host) 2754 { 2755 struct mmc_host *mmc; 2756 u32 caps[2] = {0, 0}; 2757 u32 max_current_caps; 2758 unsigned int ocr_avail; 2759 int ret; 2760 2761 WARN_ON(host == NULL); 2762 if (host == NULL) 2763 return -EINVAL; 2764 2765 mmc = host->mmc; 2766 2767 if (debug_quirks) 2768 host->quirks = debug_quirks; 2769 if (debug_quirks2) 2770 host->quirks2 = debug_quirks2; 2771 2772 sdhci_do_reset(host, SDHCI_RESET_ALL); 2773 2774 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 2775 host->version = (host->version & SDHCI_SPEC_VER_MASK) 2776 >> SDHCI_SPEC_VER_SHIFT; 2777 if (host->version > SDHCI_SPEC_300) { 2778 pr_err("%s: Unknown controller version (%d). " 2779 "You may experience problems.\n", mmc_hostname(mmc), 2780 host->version); 2781 } 2782 2783 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2784 sdhci_readl(host, SDHCI_CAPABILITIES); 2785 2786 if (host->version >= SDHCI_SPEC_300) 2787 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2788 host->caps1 : 2789 sdhci_readl(host, SDHCI_CAPABILITIES_1); 2790 2791 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2792 host->flags |= SDHCI_USE_SDMA; 2793 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2794 DBG("Controller doesn't have SDMA capability\n"); 2795 else 2796 host->flags |= SDHCI_USE_SDMA; 2797 2798 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2799 (host->flags & SDHCI_USE_SDMA)) { 2800 DBG("Disabling DMA as it is marked broken\n"); 2801 host->flags &= ~SDHCI_USE_SDMA; 2802 } 2803 2804 if ((host->version >= SDHCI_SPEC_200) && 2805 (caps[0] & SDHCI_CAN_DO_ADMA2)) 2806 host->flags |= SDHCI_USE_ADMA; 2807 2808 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 2809 (host->flags & SDHCI_USE_ADMA)) { 2810 DBG("Disabling ADMA as it is marked broken\n"); 2811 host->flags &= ~SDHCI_USE_ADMA; 2812 } 2813 2814 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2815 if (host->ops->enable_dma) { 2816 if (host->ops->enable_dma(host)) { 2817 pr_warning("%s: No suitable DMA " 2818 "available. Falling back to PIO.\n", 2819 mmc_hostname(mmc)); 2820 host->flags &= 2821 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 2822 } 2823 } 2824 } 2825 2826 if (host->flags & SDHCI_USE_ADMA) { 2827 /* 2828 * We need to allocate descriptors for all sg entries 2829 * (128) and potentially one alignment transfer for 2830 * each of those entries. 2831 */ 2832 host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc), 2833 ADMA_SIZE, &host->adma_addr, 2834 GFP_KERNEL); 2835 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 2836 if (!host->adma_desc || !host->align_buffer) { 2837 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, 2838 host->adma_desc, host->adma_addr); 2839 kfree(host->align_buffer); 2840 pr_warning("%s: Unable to allocate ADMA " 2841 "buffers. Falling back to standard DMA.\n", 2842 mmc_hostname(mmc)); 2843 host->flags &= ~SDHCI_USE_ADMA; 2844 host->adma_desc = NULL; 2845 host->align_buffer = NULL; 2846 } else if (host->adma_addr & 3) { 2847 pr_warning("%s: unable to allocate aligned ADMA descriptor\n", 2848 mmc_hostname(mmc)); 2849 host->flags &= ~SDHCI_USE_ADMA; 2850 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, 2851 host->adma_desc, host->adma_addr); 2852 kfree(host->align_buffer); 2853 host->adma_desc = NULL; 2854 host->align_buffer = NULL; 2855 } 2856 } 2857 2858 /* 2859 * If we use DMA, then it's up to the caller to set the DMA 2860 * mask, but PIO does not need the hw shim so we set a new 2861 * mask here in that case. 2862 */ 2863 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 2864 host->dma_mask = DMA_BIT_MASK(64); 2865 mmc_dev(host->mmc)->dma_mask = &host->dma_mask; 2866 } 2867 2868 if (host->version >= SDHCI_SPEC_300) 2869 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2870 >> SDHCI_CLOCK_BASE_SHIFT; 2871 else 2872 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2873 >> SDHCI_CLOCK_BASE_SHIFT; 2874 2875 host->max_clk *= 1000000; 2876 if (host->max_clk == 0 || host->quirks & 2877 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 2878 if (!host->ops->get_max_clock) { 2879 pr_err("%s: Hardware doesn't specify base clock " 2880 "frequency.\n", mmc_hostname(mmc)); 2881 return -ENODEV; 2882 } 2883 host->max_clk = host->ops->get_max_clock(host); 2884 } 2885 2886 /* 2887 * In case of Host Controller v3.00, find out whether clock 2888 * multiplier is supported. 2889 */ 2890 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2891 SDHCI_CLOCK_MUL_SHIFT; 2892 2893 /* 2894 * In case the value in Clock Multiplier is 0, then programmable 2895 * clock mode is not supported, otherwise the actual clock 2896 * multiplier is one more than the value of Clock Multiplier 2897 * in the Capabilities Register. 2898 */ 2899 if (host->clk_mul) 2900 host->clk_mul += 1; 2901 2902 /* 2903 * Set host parameters. 2904 */ 2905 mmc->ops = &sdhci_ops; 2906 mmc->f_max = host->max_clk; 2907 if (host->ops->get_min_clock) 2908 mmc->f_min = host->ops->get_min_clock(host); 2909 else if (host->version >= SDHCI_SPEC_300) { 2910 if (host->clk_mul) { 2911 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2912 mmc->f_max = host->max_clk * host->clk_mul; 2913 } else 2914 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2915 } else 2916 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 2917 2918 host->timeout_clk = 2919 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 2920 if (host->timeout_clk == 0) { 2921 if (host->ops->get_timeout_clock) { 2922 host->timeout_clk = host->ops->get_timeout_clock(host); 2923 } else if (!(host->quirks & 2924 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 2925 pr_err("%s: Hardware doesn't specify timeout clock " 2926 "frequency.\n", mmc_hostname(mmc)); 2927 return -ENODEV; 2928 } 2929 } 2930 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2931 host->timeout_clk *= 1000; 2932 2933 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 2934 host->timeout_clk = mmc->f_max / 1000; 2935 2936 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; 2937 2938 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2939 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2940 2941 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2942 host->flags |= SDHCI_AUTO_CMD12; 2943 2944 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 2945 if ((host->version >= SDHCI_SPEC_300) && 2946 ((host->flags & SDHCI_USE_ADMA) || 2947 !(host->flags & SDHCI_USE_SDMA))) { 2948 host->flags |= SDHCI_AUTO_CMD23; 2949 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 2950 } else { 2951 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 2952 } 2953 2954 /* 2955 * A controller may support 8-bit width, but the board itself 2956 * might not have the pins brought out. Boards that support 2957 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 2958 * their platform code before calling sdhci_add_host(), and we 2959 * won't assume 8-bit width for hosts without that CAP. 2960 */ 2961 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 2962 mmc->caps |= MMC_CAP_4_BIT_DATA; 2963 2964 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 2965 mmc->caps &= ~MMC_CAP_CMD23; 2966 2967 if (caps[0] & SDHCI_CAN_DO_HISPD) 2968 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 2969 2970 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 2971 !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) 2972 mmc->caps |= MMC_CAP_NEEDS_POLL; 2973 2974 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 2975 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc"); 2976 if (IS_ERR_OR_NULL(host->vqmmc)) { 2977 if (PTR_ERR(host->vqmmc) < 0) { 2978 pr_info("%s: no vqmmc regulator found\n", 2979 mmc_hostname(mmc)); 2980 host->vqmmc = NULL; 2981 } 2982 } else { 2983 ret = regulator_enable(host->vqmmc); 2984 if (!regulator_is_supported_voltage(host->vqmmc, 1700000, 2985 1950000)) 2986 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 2987 SDHCI_SUPPORT_SDR50 | 2988 SDHCI_SUPPORT_DDR50); 2989 if (ret) { 2990 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 2991 mmc_hostname(mmc), ret); 2992 host->vqmmc = NULL; 2993 } 2994 } 2995 2996 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 2997 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 2998 SDHCI_SUPPORT_DDR50); 2999 3000 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 3001 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3002 SDHCI_SUPPORT_DDR50)) 3003 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3004 3005 /* SDR104 supports also implies SDR50 support */ 3006 if (caps[1] & SDHCI_SUPPORT_SDR104) { 3007 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3008 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3009 * field can be promoted to support HS200. 3010 */ 3011 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3012 mmc->caps2 |= MMC_CAP2_HS200; 3013 } else if (caps[1] & SDHCI_SUPPORT_SDR50) 3014 mmc->caps |= MMC_CAP_UHS_SDR50; 3015 3016 if ((caps[1] & SDHCI_SUPPORT_DDR50) && 3017 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3018 mmc->caps |= MMC_CAP_UHS_DDR50; 3019 3020 /* Does the host need tuning for SDR50? */ 3021 if (caps[1] & SDHCI_USE_SDR50_TUNING) 3022 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3023 3024 /* Does the host need tuning for SDR104 / HS200? */ 3025 if (mmc->caps2 & MMC_CAP2_HS200) 3026 host->flags |= SDHCI_SDR104_NEEDS_TUNING; 3027 3028 /* Driver Type(s) (A, C, D) supported by the host */ 3029 if (caps[1] & SDHCI_DRIVER_TYPE_A) 3030 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3031 if (caps[1] & SDHCI_DRIVER_TYPE_C) 3032 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3033 if (caps[1] & SDHCI_DRIVER_TYPE_D) 3034 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3035 3036 /* Initial value for re-tuning timer count */ 3037 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3038 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3039 3040 /* 3041 * In case Re-tuning Timer is not disabled, the actual value of 3042 * re-tuning timer will be 2 ^ (n - 1). 3043 */ 3044 if (host->tuning_count) 3045 host->tuning_count = 1 << (host->tuning_count - 1); 3046 3047 /* Re-tuning mode supported by the Host Controller */ 3048 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 3049 SDHCI_RETUNING_MODE_SHIFT; 3050 3051 ocr_avail = 0; 3052 3053 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc"); 3054 if (IS_ERR_OR_NULL(host->vmmc)) { 3055 if (PTR_ERR(host->vmmc) < 0) { 3056 pr_info("%s: no vmmc regulator found\n", 3057 mmc_hostname(mmc)); 3058 host->vmmc = NULL; 3059 } 3060 } 3061 3062 #ifdef CONFIG_REGULATOR 3063 /* 3064 * Voltage range check makes sense only if regulator reports 3065 * any voltage value. 3066 */ 3067 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) { 3068 ret = regulator_is_supported_voltage(host->vmmc, 2700000, 3069 3600000); 3070 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330))) 3071 caps[0] &= ~SDHCI_CAN_VDD_330; 3072 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300))) 3073 caps[0] &= ~SDHCI_CAN_VDD_300; 3074 ret = regulator_is_supported_voltage(host->vmmc, 1700000, 3075 1950000); 3076 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180))) 3077 caps[0] &= ~SDHCI_CAN_VDD_180; 3078 } 3079 #endif /* CONFIG_REGULATOR */ 3080 3081 /* 3082 * According to SD Host Controller spec v3.00, if the Host System 3083 * can afford more than 150mA, Host Driver should set XPC to 1. Also 3084 * the value is meaningful only if Voltage Support in the Capabilities 3085 * register is set. The actual current value is 4 times the register 3086 * value. 3087 */ 3088 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3089 if (!max_current_caps && host->vmmc) { 3090 u32 curr = regulator_get_current_limit(host->vmmc); 3091 if (curr > 0) { 3092 3093 /* convert to SDHCI_MAX_CURRENT format */ 3094 curr = curr/1000; /* convert to mA */ 3095 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3096 3097 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3098 max_current_caps = 3099 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3100 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3101 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3102 } 3103 } 3104 3105 if (caps[0] & SDHCI_CAN_VDD_330) { 3106 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3107 3108 mmc->max_current_330 = ((max_current_caps & 3109 SDHCI_MAX_CURRENT_330_MASK) >> 3110 SDHCI_MAX_CURRENT_330_SHIFT) * 3111 SDHCI_MAX_CURRENT_MULTIPLIER; 3112 } 3113 if (caps[0] & SDHCI_CAN_VDD_300) { 3114 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3115 3116 mmc->max_current_300 = ((max_current_caps & 3117 SDHCI_MAX_CURRENT_300_MASK) >> 3118 SDHCI_MAX_CURRENT_300_SHIFT) * 3119 SDHCI_MAX_CURRENT_MULTIPLIER; 3120 } 3121 if (caps[0] & SDHCI_CAN_VDD_180) { 3122 ocr_avail |= MMC_VDD_165_195; 3123 3124 mmc->max_current_180 = ((max_current_caps & 3125 SDHCI_MAX_CURRENT_180_MASK) >> 3126 SDHCI_MAX_CURRENT_180_SHIFT) * 3127 SDHCI_MAX_CURRENT_MULTIPLIER; 3128 } 3129 3130 if (host->ocr_mask) 3131 ocr_avail = host->ocr_mask; 3132 3133 mmc->ocr_avail = ocr_avail; 3134 mmc->ocr_avail_sdio = ocr_avail; 3135 if (host->ocr_avail_sdio) 3136 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3137 mmc->ocr_avail_sd = ocr_avail; 3138 if (host->ocr_avail_sd) 3139 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3140 else /* normal SD controllers don't support 1.8V */ 3141 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3142 mmc->ocr_avail_mmc = ocr_avail; 3143 if (host->ocr_avail_mmc) 3144 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3145 3146 if (mmc->ocr_avail == 0) { 3147 pr_err("%s: Hardware doesn't report any " 3148 "support voltages.\n", mmc_hostname(mmc)); 3149 return -ENODEV; 3150 } 3151 3152 spin_lock_init(&host->lock); 3153 3154 /* 3155 * Maximum number of segments. Depends on if the hardware 3156 * can do scatter/gather or not. 3157 */ 3158 if (host->flags & SDHCI_USE_ADMA) 3159 mmc->max_segs = 128; 3160 else if (host->flags & SDHCI_USE_SDMA) 3161 mmc->max_segs = 1; 3162 else /* PIO */ 3163 mmc->max_segs = 128; 3164 3165 /* 3166 * Maximum number of sectors in one transfer. Limited by DMA boundary 3167 * size (512KiB). 3168 */ 3169 mmc->max_req_size = 524288; 3170 3171 /* 3172 * Maximum segment size. Could be one segment with the maximum number 3173 * of bytes. When doing hardware scatter/gather, each entry cannot 3174 * be larger than 64 KiB though. 3175 */ 3176 if (host->flags & SDHCI_USE_ADMA) { 3177 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3178 mmc->max_seg_size = 65535; 3179 else 3180 mmc->max_seg_size = 65536; 3181 } else { 3182 mmc->max_seg_size = mmc->max_req_size; 3183 } 3184 3185 /* 3186 * Maximum block size. This varies from controller to controller and 3187 * is specified in the capabilities register. 3188 */ 3189 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3190 mmc->max_blk_size = 2; 3191 } else { 3192 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 3193 SDHCI_MAX_BLOCK_SHIFT; 3194 if (mmc->max_blk_size >= 3) { 3195 pr_warning("%s: Invalid maximum block size, " 3196 "assuming 512 bytes\n", mmc_hostname(mmc)); 3197 mmc->max_blk_size = 0; 3198 } 3199 } 3200 3201 mmc->max_blk_size = 512 << mmc->max_blk_size; 3202 3203 /* 3204 * Maximum block count. 3205 */ 3206 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3207 3208 /* 3209 * Init tasklets. 3210 */ 3211 tasklet_init(&host->finish_tasklet, 3212 sdhci_tasklet_finish, (unsigned long)host); 3213 3214 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3215 3216 if (host->version >= SDHCI_SPEC_300) { 3217 init_waitqueue_head(&host->buf_ready_int); 3218 3219 /* Initialize re-tuning timer */ 3220 init_timer(&host->tuning_timer); 3221 host->tuning_timer.data = (unsigned long)host; 3222 host->tuning_timer.function = sdhci_tuning_timer; 3223 } 3224 3225 sdhci_init(host, 0); 3226 3227 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3228 IRQF_SHARED, mmc_hostname(mmc), host); 3229 if (ret) { 3230 pr_err("%s: Failed to request IRQ %d: %d\n", 3231 mmc_hostname(mmc), host->irq, ret); 3232 goto untasklet; 3233 } 3234 3235 #ifdef CONFIG_MMC_DEBUG 3236 sdhci_dumpregs(host); 3237 #endif 3238 3239 #ifdef SDHCI_USE_LEDS_CLASS 3240 snprintf(host->led_name, sizeof(host->led_name), 3241 "%s::", mmc_hostname(mmc)); 3242 host->led.name = host->led_name; 3243 host->led.brightness = LED_OFF; 3244 host->led.default_trigger = mmc_hostname(mmc); 3245 host->led.brightness_set = sdhci_led_control; 3246 3247 ret = led_classdev_register(mmc_dev(mmc), &host->led); 3248 if (ret) { 3249 pr_err("%s: Failed to register LED device: %d\n", 3250 mmc_hostname(mmc), ret); 3251 goto reset; 3252 } 3253 #endif 3254 3255 mmiowb(); 3256 3257 mmc_add_host(mmc); 3258 3259 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3260 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3261 (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 3262 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3263 3264 sdhci_enable_card_detection(host); 3265 3266 return 0; 3267 3268 #ifdef SDHCI_USE_LEDS_CLASS 3269 reset: 3270 sdhci_do_reset(host, SDHCI_RESET_ALL); 3271 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3272 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3273 free_irq(host->irq, host); 3274 #endif 3275 untasklet: 3276 tasklet_kill(&host->finish_tasklet); 3277 3278 return ret; 3279 } 3280 3281 EXPORT_SYMBOL_GPL(sdhci_add_host); 3282 3283 void sdhci_remove_host(struct sdhci_host *host, int dead) 3284 { 3285 unsigned long flags; 3286 3287 if (dead) { 3288 spin_lock_irqsave(&host->lock, flags); 3289 3290 host->flags |= SDHCI_DEVICE_DEAD; 3291 3292 if (host->mrq) { 3293 pr_err("%s: Controller removed during " 3294 " transfer!\n", mmc_hostname(host->mmc)); 3295 3296 host->mrq->cmd->error = -ENOMEDIUM; 3297 tasklet_schedule(&host->finish_tasklet); 3298 } 3299 3300 spin_unlock_irqrestore(&host->lock, flags); 3301 } 3302 3303 sdhci_disable_card_detection(host); 3304 3305 mmc_remove_host(host->mmc); 3306 3307 #ifdef SDHCI_USE_LEDS_CLASS 3308 led_classdev_unregister(&host->led); 3309 #endif 3310 3311 if (!dead) 3312 sdhci_do_reset(host, SDHCI_RESET_ALL); 3313 3314 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3315 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3316 free_irq(host->irq, host); 3317 3318 del_timer_sync(&host->timer); 3319 3320 tasklet_kill(&host->finish_tasklet); 3321 3322 if (host->vmmc) { 3323 regulator_disable(host->vmmc); 3324 regulator_put(host->vmmc); 3325 } 3326 3327 if (host->vqmmc) { 3328 regulator_disable(host->vqmmc); 3329 regulator_put(host->vqmmc); 3330 } 3331 3332 if (host->adma_desc) 3333 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE, 3334 host->adma_desc, host->adma_addr); 3335 kfree(host->align_buffer); 3336 3337 host->adma_desc = NULL; 3338 host->align_buffer = NULL; 3339 } 3340 3341 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3342 3343 void sdhci_free_host(struct sdhci_host *host) 3344 { 3345 mmc_free_host(host->mmc); 3346 } 3347 3348 EXPORT_SYMBOL_GPL(sdhci_free_host); 3349 3350 /*****************************************************************************\ 3351 * * 3352 * Driver init/exit * 3353 * * 3354 \*****************************************************************************/ 3355 3356 static int __init sdhci_drv_init(void) 3357 { 3358 pr_info(DRIVER_NAME 3359 ": Secure Digital Host Controller Interface driver\n"); 3360 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3361 3362 return 0; 3363 } 3364 3365 static void __exit sdhci_drv_exit(void) 3366 { 3367 } 3368 3369 module_init(sdhci_drv_init); 3370 module_exit(sdhci_drv_exit); 3371 3372 module_param(debug_quirks, uint, 0444); 3373 module_param(debug_quirks2, uint, 0444); 3374 3375 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3376 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3377 MODULE_LICENSE("GPL"); 3378 3379 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3380 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3381