sor.c (b299221ca99683e50ea03ac8ca638f9f43d2a59c) sor.c (618dee3941a43d8d4f762a7af99bcb59baba2bc5)
1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

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168
169 const struct tegra_sor_soc *soc;
170 void __iomem *regs;
171
172 struct reset_control *rst;
173 struct clk *clk_parent;
174 struct clk *clk_brick;
175 struct clk *clk_safe;
1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

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168
169 const struct tegra_sor_soc *soc;
170 void __iomem *regs;
171
172 struct reset_control *rst;
173 struct clk *clk_parent;
174 struct clk *clk_brick;
175 struct clk *clk_safe;
176 struct clk *clk_src;
176 struct clk *clk_dp;
177 struct clk *clk;
178
179 struct drm_dp_aux *aux;
180
181 struct drm_info_list *debugfs_files;
182 struct drm_minor *minor;
183 struct dentry *debugfs;

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2096 SOR_XBAR_CTRL_LINK0_XSEL(2, 0) |
2097 SOR_XBAR_CTRL_LINK0_XSEL(1, 1) |
2098 SOR_XBAR_CTRL_LINK0_XSEL(0, 2);
2099 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2100
2101 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2102
2103 /* switch to parent clock */
177 struct clk *clk_dp;
178 struct clk *clk;
179
180 struct drm_dp_aux *aux;
181
182 struct drm_info_list *debugfs_files;
183 struct drm_minor *minor;
184 struct dentry *debugfs;

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2097 SOR_XBAR_CTRL_LINK0_XSEL(2, 0) |
2098 SOR_XBAR_CTRL_LINK0_XSEL(1, 1) |
2099 SOR_XBAR_CTRL_LINK0_XSEL(0, 2);
2100 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2101
2102 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2103
2104 /* switch to parent clock */
2104 err = tegra_sor_set_parent_clock(sor, sor->clk_parent);
2105 err = clk_set_parent(sor->clk_src, sor->clk_parent);
2105 if (err < 0)
2106 if (err < 0)
2107 dev_err(sor->dev, "failed to set source clock: %d\n", err);
2108
2109 err = tegra_sor_set_parent_clock(sor, sor->clk_src);
2110 if (err < 0)
2106 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2107
2108 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2109
2110 /* XXX is this the proper check? */
2111 if (mode->clock < 75000)
2112 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2113

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2590
2591 sor->clk = devm_clk_get(&pdev->dev, NULL);
2592 if (IS_ERR(sor->clk)) {
2593 err = PTR_ERR(sor->clk);
2594 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
2595 goto remove;
2596 }
2597
2111 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2112
2113 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2114
2115 /* XXX is this the proper check? */
2116 if (mode->clock < 75000)
2117 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2118

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2595
2596 sor->clk = devm_clk_get(&pdev->dev, NULL);
2597 if (IS_ERR(sor->clk)) {
2598 err = PTR_ERR(sor->clk);
2599 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
2600 goto remove;
2601 }
2602
2603 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
2604 sor->clk_src = devm_clk_get(&pdev->dev, "source");
2605 if (IS_ERR(sor->clk_src)) {
2606 err = PTR_ERR(sor->clk_src);
2607 dev_err(sor->dev, "failed to get source clock: %d\n",
2608 err);
2609 goto remove;
2610 }
2611 }
2612
2598 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
2599 if (IS_ERR(sor->clk_parent)) {
2600 err = PTR_ERR(sor->clk_parent);
2601 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
2602 goto remove;
2603 }
2604
2605 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");

--- 128 unchanged lines hidden --- 		2613 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
2614 if (IS_ERR(sor->clk_parent)) {
2615 err = PTR_ERR(sor->clk_parent);
2616 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
2617 goto remove;
2618 }
2619
2620 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");

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