1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/debugfs.h> 12 #include <linux/gpio.h> 13 #include <linux/io.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/reset.h> 19 20 #include <soc/tegra/pmc.h> 21 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_dp_helper.h> 24 #include <drm/drm_panel.h> 25 26 #include "dc.h" 27 #include "drm.h" 28 #include "sor.h" 29 30 #define SOR_REKEY 0x38 31 32 struct tegra_sor_hdmi_settings { 33 unsigned long frequency; 34 35 u8 vcocap; 36 u8 ichpmp; 37 u8 loadadj; 38 u8 termadj; 39 u8 tx_pu; 40 u8 bg_vref; 41 42 u8 drive_current[4]; 43 u8 preemphasis[4]; 44 }; 45 46 #if 1 47 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 48 { 49 .frequency = 54000000, 50 .vcocap = 0x0, 51 .ichpmp = 0x1, 52 .loadadj = 0x3, 53 .termadj = 0x9, 54 .tx_pu = 0x10, 55 .bg_vref = 0x8, 56 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 57 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 58 }, { 59 .frequency = 75000000, 60 .vcocap = 0x3, 61 .ichpmp = 0x1, 62 .loadadj = 0x3, 63 .termadj = 0x9, 64 .tx_pu = 0x40, 65 .bg_vref = 0x8, 66 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 67 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 68 }, { 69 .frequency = 150000000, 70 .vcocap = 0x3, 71 .ichpmp = 0x1, 72 .loadadj = 0x3, 73 .termadj = 0x9, 74 .tx_pu = 0x66, 75 .bg_vref = 0x8, 76 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 77 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 78 }, { 79 .frequency = 300000000, 80 .vcocap = 0x3, 81 .ichpmp = 0x1, 82 .loadadj = 0x3, 83 .termadj = 0x9, 84 .tx_pu = 0x66, 85 .bg_vref = 0xa, 86 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 87 .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, 88 }, { 89 .frequency = 600000000, 90 .vcocap = 0x3, 91 .ichpmp = 0x1, 92 .loadadj = 0x3, 93 .termadj = 0x9, 94 .tx_pu = 0x66, 95 .bg_vref = 0x8, 96 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 97 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 98 }, 99 }; 100 #else 101 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 102 { 103 .frequency = 75000000, 104 .vcocap = 0x3, 105 .ichpmp = 0x1, 106 .loadadj = 0x3, 107 .termadj = 0x9, 108 .tx_pu = 0x40, 109 .bg_vref = 0x8, 110 .drive_current = { 0x29, 0x29, 0x29, 0x29 }, 111 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 112 }, { 113 .frequency = 150000000, 114 .vcocap = 0x3, 115 .ichpmp = 0x1, 116 .loadadj = 0x3, 117 .termadj = 0x9, 118 .tx_pu = 0x66, 119 .bg_vref = 0x8, 120 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 121 .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, 122 }, { 123 .frequency = 300000000, 124 .vcocap = 0x3, 125 .ichpmp = 0x6, 126 .loadadj = 0x3, 127 .termadj = 0x9, 128 .tx_pu = 0x66, 129 .bg_vref = 0xf, 130 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 131 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, 132 }, { 133 .frequency = 600000000, 134 .vcocap = 0x3, 135 .ichpmp = 0xa, 136 .loadadj = 0x3, 137 .termadj = 0xb, 138 .tx_pu = 0x66, 139 .bg_vref = 0xe, 140 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, 141 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, 142 }, 143 }; 144 #endif 145 146 struct tegra_sor_soc { 147 bool supports_edp; 148 bool supports_lvds; 149 bool supports_hdmi; 150 bool supports_dp; 151 152 const struct tegra_sor_hdmi_settings *settings; 153 unsigned int num_settings; 154 }; 155 156 struct tegra_sor; 157 158 struct tegra_sor_ops { 159 const char *name; 160 int (*probe)(struct tegra_sor *sor); 161 int (*remove)(struct tegra_sor *sor); 162 }; 163 164 struct tegra_sor { 165 struct host1x_client client; 166 struct tegra_output output; 167 struct device *dev; 168 169 const struct tegra_sor_soc *soc; 170 void __iomem *regs; 171 172 struct reset_control *rst; 173 struct clk *clk_parent; 174 struct clk *clk_brick; 175 struct clk *clk_safe; 176 struct clk *clk_dp; 177 struct clk *clk; 178 179 struct drm_dp_aux *aux; 180 181 struct drm_info_list *debugfs_files; 182 struct drm_minor *minor; 183 struct dentry *debugfs; 184 185 const struct tegra_sor_ops *ops; 186 187 /* for HDMI 2.0 */ 188 struct tegra_sor_hdmi_settings *settings; 189 unsigned int num_settings; 190 191 struct regulator *avdd_io_supply; 192 struct regulator *vdd_pll_supply; 193 struct regulator *hdmi_supply; 194 }; 195 196 struct tegra_sor_state { 197 struct drm_connector_state base; 198 199 unsigned int bpc; 200 }; 201 202 static inline struct tegra_sor_state * 203 to_sor_state(struct drm_connector_state *state) 204 { 205 return container_of(state, struct tegra_sor_state, base); 206 } 207 208 struct tegra_sor_config { 209 u32 bits_per_pixel; 210 211 u32 active_polarity; 212 u32 active_count; 213 u32 tu_size; 214 u32 active_frac; 215 u32 watermark; 216 217 u32 hblank_symbols; 218 u32 vblank_symbols; 219 }; 220 221 static inline struct tegra_sor * 222 host1x_client_to_sor(struct host1x_client *client) 223 { 224 return container_of(client, struct tegra_sor, client); 225 } 226 227 static inline struct tegra_sor *to_sor(struct tegra_output *output) 228 { 229 return container_of(output, struct tegra_sor, output); 230 } 231 232 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) 233 { 234 return readl(sor->regs + (offset << 2)); 235 } 236 237 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, 238 unsigned long offset) 239 { 240 writel(value, sor->regs + (offset << 2)); 241 } 242 243 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) 244 { 245 int err; 246 247 clk_disable_unprepare(sor->clk); 248 249 err = clk_set_parent(sor->clk, parent); 250 if (err < 0) 251 return err; 252 253 err = clk_prepare_enable(sor->clk); 254 if (err < 0) 255 return err; 256 257 return 0; 258 } 259 260 struct tegra_clk_sor_brick { 261 struct clk_hw hw; 262 struct tegra_sor *sor; 263 }; 264 265 static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw) 266 { 267 return container_of(hw, struct tegra_clk_sor_brick, hw); 268 } 269 270 static const char * const tegra_clk_sor_brick_parents[] = { 271 "pll_d2_out0", "pll_dp" 272 }; 273 274 static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index) 275 { 276 struct tegra_clk_sor_brick *brick = to_brick(hw); 277 struct tegra_sor *sor = brick->sor; 278 u32 value; 279 280 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 281 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 282 283 switch (index) { 284 case 0: 285 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 286 break; 287 288 case 1: 289 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 290 break; 291 } 292 293 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 294 295 return 0; 296 } 297 298 static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw) 299 { 300 struct tegra_clk_sor_brick *brick = to_brick(hw); 301 struct tegra_sor *sor = brick->sor; 302 u8 parent = U8_MAX; 303 u32 value; 304 305 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 306 307 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { 308 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: 309 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK: 310 parent = 0; 311 break; 312 313 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK: 314 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK: 315 parent = 1; 316 break; 317 } 318 319 return parent; 320 } 321 322 static const struct clk_ops tegra_clk_sor_brick_ops = { 323 .set_parent = tegra_clk_sor_brick_set_parent, 324 .get_parent = tegra_clk_sor_brick_get_parent, 325 }; 326 327 static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor, 328 const char *name) 329 { 330 struct tegra_clk_sor_brick *brick; 331 struct clk_init_data init; 332 struct clk *clk; 333 334 brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL); 335 if (!brick) 336 return ERR_PTR(-ENOMEM); 337 338 brick->sor = sor; 339 340 init.name = name; 341 init.flags = 0; 342 init.parent_names = tegra_clk_sor_brick_parents; 343 init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents); 344 init.ops = &tegra_clk_sor_brick_ops; 345 346 brick->hw.init = &init; 347 348 clk = devm_clk_register(sor->dev, &brick->hw); 349 if (IS_ERR(clk)) 350 kfree(brick); 351 352 return clk; 353 } 354 355 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, 356 struct drm_dp_link *link) 357 { 358 unsigned int i; 359 u8 pattern; 360 u32 value; 361 int err; 362 363 /* setup lane parameters */ 364 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | 365 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | 366 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | 367 SOR_LANE_DRIVE_CURRENT_LANE0(0x40); 368 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 369 370 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | 371 SOR_LANE_PREEMPHASIS_LANE2(0x0f) | 372 SOR_LANE_PREEMPHASIS_LANE1(0x0f) | 373 SOR_LANE_PREEMPHASIS_LANE0(0x0f); 374 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 375 376 value = SOR_LANE_POSTCURSOR_LANE3(0x00) | 377 SOR_LANE_POSTCURSOR_LANE2(0x00) | 378 SOR_LANE_POSTCURSOR_LANE1(0x00) | 379 SOR_LANE_POSTCURSOR_LANE0(0x00); 380 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); 381 382 /* disable LVDS mode */ 383 tegra_sor_writel(sor, 0, SOR_LVDS); 384 385 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 386 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 387 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 388 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ 389 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 390 391 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 392 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 393 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; 394 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 395 396 usleep_range(10, 100); 397 398 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 399 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 400 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 401 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 402 403 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); 404 if (err < 0) 405 return err; 406 407 for (i = 0, value = 0; i < link->num_lanes; i++) { 408 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 409 SOR_DP_TPG_SCRAMBLER_NONE | 410 SOR_DP_TPG_PATTERN_TRAIN1; 411 value = (value << 8) | lane; 412 } 413 414 tegra_sor_writel(sor, value, SOR_DP_TPG); 415 416 pattern = DP_TRAINING_PATTERN_1; 417 418 err = drm_dp_aux_train(sor->aux, link, pattern); 419 if (err < 0) 420 return err; 421 422 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 423 value |= SOR_DP_SPARE_SEQ_ENABLE; 424 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 425 value |= SOR_DP_SPARE_MACRO_SOR_CLK; 426 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 427 428 for (i = 0, value = 0; i < link->num_lanes; i++) { 429 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 430 SOR_DP_TPG_SCRAMBLER_NONE | 431 SOR_DP_TPG_PATTERN_TRAIN2; 432 value = (value << 8) | lane; 433 } 434 435 tegra_sor_writel(sor, value, SOR_DP_TPG); 436 437 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; 438 439 err = drm_dp_aux_train(sor->aux, link, pattern); 440 if (err < 0) 441 return err; 442 443 for (i = 0, value = 0; i < link->num_lanes; i++) { 444 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 445 SOR_DP_TPG_SCRAMBLER_GALIOS | 446 SOR_DP_TPG_PATTERN_NONE; 447 value = (value << 8) | lane; 448 } 449 450 tegra_sor_writel(sor, value, SOR_DP_TPG); 451 452 pattern = DP_TRAINING_PATTERN_DISABLE; 453 454 err = drm_dp_aux_train(sor->aux, link, pattern); 455 if (err < 0) 456 return err; 457 458 return 0; 459 } 460 461 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) 462 { 463 u32 mask = 0x08, adj = 0, value; 464 465 /* enable pad calibration logic */ 466 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 467 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 468 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 469 470 value = tegra_sor_readl(sor, SOR_PLL1); 471 value |= SOR_PLL1_TMDS_TERM; 472 tegra_sor_writel(sor, value, SOR_PLL1); 473 474 while (mask) { 475 adj |= mask; 476 477 value = tegra_sor_readl(sor, SOR_PLL1); 478 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 479 value |= SOR_PLL1_TMDS_TERMADJ(adj); 480 tegra_sor_writel(sor, value, SOR_PLL1); 481 482 usleep_range(100, 200); 483 484 value = tegra_sor_readl(sor, SOR_PLL1); 485 if (value & SOR_PLL1_TERM_COMPOUT) 486 adj &= ~mask; 487 488 mask >>= 1; 489 } 490 491 value = tegra_sor_readl(sor, SOR_PLL1); 492 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 493 value |= SOR_PLL1_TMDS_TERMADJ(adj); 494 tegra_sor_writel(sor, value, SOR_PLL1); 495 496 /* disable pad calibration logic */ 497 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 498 value |= SOR_DP_PADCTL_PAD_CAL_PD; 499 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 500 } 501 502 static void tegra_sor_super_update(struct tegra_sor *sor) 503 { 504 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 505 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); 506 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 507 } 508 509 static void tegra_sor_update(struct tegra_sor *sor) 510 { 511 tegra_sor_writel(sor, 0, SOR_STATE0); 512 tegra_sor_writel(sor, 1, SOR_STATE0); 513 tegra_sor_writel(sor, 0, SOR_STATE0); 514 } 515 516 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 517 { 518 u32 value; 519 520 value = tegra_sor_readl(sor, SOR_PWM_DIV); 521 value &= ~SOR_PWM_DIV_MASK; 522 value |= 0x400; /* period */ 523 tegra_sor_writel(sor, value, SOR_PWM_DIV); 524 525 value = tegra_sor_readl(sor, SOR_PWM_CTL); 526 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 527 value |= 0x400; /* duty cycle */ 528 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 529 value |= SOR_PWM_CTL_TRIGGER; 530 tegra_sor_writel(sor, value, SOR_PWM_CTL); 531 532 timeout = jiffies + msecs_to_jiffies(timeout); 533 534 while (time_before(jiffies, timeout)) { 535 value = tegra_sor_readl(sor, SOR_PWM_CTL); 536 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 537 return 0; 538 539 usleep_range(25, 100); 540 } 541 542 return -ETIMEDOUT; 543 } 544 545 static int tegra_sor_attach(struct tegra_sor *sor) 546 { 547 unsigned long value, timeout; 548 549 /* wake up in normal mode */ 550 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 551 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 552 value |= SOR_SUPER_STATE_MODE_NORMAL; 553 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 554 tegra_sor_super_update(sor); 555 556 /* attach */ 557 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 558 value |= SOR_SUPER_STATE_ATTACHED; 559 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 560 tegra_sor_super_update(sor); 561 562 timeout = jiffies + msecs_to_jiffies(250); 563 564 while (time_before(jiffies, timeout)) { 565 value = tegra_sor_readl(sor, SOR_TEST); 566 if ((value & SOR_TEST_ATTACHED) != 0) 567 return 0; 568 569 usleep_range(25, 100); 570 } 571 572 return -ETIMEDOUT; 573 } 574 575 static int tegra_sor_wakeup(struct tegra_sor *sor) 576 { 577 unsigned long value, timeout; 578 579 timeout = jiffies + msecs_to_jiffies(250); 580 581 /* wait for head to wake up */ 582 while (time_before(jiffies, timeout)) { 583 value = tegra_sor_readl(sor, SOR_TEST); 584 value &= SOR_TEST_HEAD_MODE_MASK; 585 586 if (value == SOR_TEST_HEAD_MODE_AWAKE) 587 return 0; 588 589 usleep_range(25, 100); 590 } 591 592 return -ETIMEDOUT; 593 } 594 595 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 596 { 597 u32 value; 598 599 value = tegra_sor_readl(sor, SOR_PWR); 600 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 601 tegra_sor_writel(sor, value, SOR_PWR); 602 603 timeout = jiffies + msecs_to_jiffies(timeout); 604 605 while (time_before(jiffies, timeout)) { 606 value = tegra_sor_readl(sor, SOR_PWR); 607 if ((value & SOR_PWR_TRIGGER) == 0) 608 return 0; 609 610 usleep_range(25, 100); 611 } 612 613 return -ETIMEDOUT; 614 } 615 616 struct tegra_sor_params { 617 /* number of link clocks per line */ 618 unsigned int num_clocks; 619 /* ratio between input and output */ 620 u64 ratio; 621 /* precision factor */ 622 u64 precision; 623 624 unsigned int active_polarity; 625 unsigned int active_count; 626 unsigned int active_frac; 627 unsigned int tu_size; 628 unsigned int error; 629 }; 630 631 static int tegra_sor_compute_params(struct tegra_sor *sor, 632 struct tegra_sor_params *params, 633 unsigned int tu_size) 634 { 635 u64 active_sym, active_count, frac, approx; 636 u32 active_polarity, active_frac = 0; 637 const u64 f = params->precision; 638 s64 error; 639 640 active_sym = params->ratio * tu_size; 641 active_count = div_u64(active_sym, f) * f; 642 frac = active_sym - active_count; 643 644 /* fraction < 0.5 */ 645 if (frac >= (f / 2)) { 646 active_polarity = 1; 647 frac = f - frac; 648 } else { 649 active_polarity = 0; 650 } 651 652 if (frac != 0) { 653 frac = div_u64(f * f, frac); /* 1/fraction */ 654 if (frac <= (15 * f)) { 655 active_frac = div_u64(frac, f); 656 657 /* round up */ 658 if (active_polarity) 659 active_frac++; 660 } else { 661 active_frac = active_polarity ? 1 : 15; 662 } 663 } 664 665 if (active_frac == 1) 666 active_polarity = 0; 667 668 if (active_polarity == 1) { 669 if (active_frac) { 670 approx = active_count + (active_frac * (f - 1)) * f; 671 approx = div_u64(approx, active_frac * f); 672 } else { 673 approx = active_count + f; 674 } 675 } else { 676 if (active_frac) 677 approx = active_count + div_u64(f, active_frac); 678 else 679 approx = active_count; 680 } 681 682 error = div_s64(active_sym - approx, tu_size); 683 error *= params->num_clocks; 684 685 if (error <= 0 && abs(error) < params->error) { 686 params->active_count = div_u64(active_count, f); 687 params->active_polarity = active_polarity; 688 params->active_frac = active_frac; 689 params->error = abs(error); 690 params->tu_size = tu_size; 691 692 if (error == 0) 693 return true; 694 } 695 696 return false; 697 } 698 699 static int tegra_sor_compute_config(struct tegra_sor *sor, 700 const struct drm_display_mode *mode, 701 struct tegra_sor_config *config, 702 struct drm_dp_link *link) 703 { 704 const u64 f = 100000, link_rate = link->rate * 1000; 705 const u64 pclk = mode->clock * 1000; 706 u64 input, output, watermark, num; 707 struct tegra_sor_params params; 708 u32 num_syms_per_line; 709 unsigned int i; 710 711 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) 712 return -EINVAL; 713 714 output = link_rate * 8 * link->num_lanes; 715 input = pclk * config->bits_per_pixel; 716 717 if (input >= output) 718 return -ERANGE; 719 720 memset(¶ms, 0, sizeof(params)); 721 params.ratio = div64_u64(input * f, output); 722 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 723 params.precision = f; 724 params.error = 64 * f; 725 params.tu_size = 64; 726 727 for (i = params.tu_size; i >= 32; i--) 728 if (tegra_sor_compute_params(sor, ¶ms, i)) 729 break; 730 731 if (params.active_frac == 0) { 732 config->active_polarity = 0; 733 config->active_count = params.active_count; 734 735 if (!params.active_polarity) 736 config->active_count--; 737 738 config->tu_size = params.tu_size; 739 config->active_frac = 1; 740 } else { 741 config->active_polarity = params.active_polarity; 742 config->active_count = params.active_count; 743 config->active_frac = params.active_frac; 744 config->tu_size = params.tu_size; 745 } 746 747 dev_dbg(sor->dev, 748 "polarity: %d active count: %d tu size: %d active frac: %d\n", 749 config->active_polarity, config->active_count, 750 config->tu_size, config->active_frac); 751 752 watermark = params.ratio * config->tu_size * (f - params.ratio); 753 watermark = div_u64(watermark, f); 754 755 watermark = div_u64(watermark + params.error, f); 756 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 757 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 758 (link->num_lanes * 8); 759 760 if (config->watermark > 30) { 761 config->watermark = 30; 762 dev_err(sor->dev, 763 "unable to compute TU size, forcing watermark to %u\n", 764 config->watermark); 765 } else if (config->watermark > num_syms_per_line) { 766 config->watermark = num_syms_per_line; 767 dev_err(sor->dev, "watermark too high, forcing to %u\n", 768 config->watermark); 769 } 770 771 /* compute the number of symbols per horizontal blanking interval */ 772 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 773 config->hblank_symbols = div_u64(num, pclk); 774 775 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 776 config->hblank_symbols -= 3; 777 778 config->hblank_symbols -= 12 / link->num_lanes; 779 780 /* compute the number of symbols per vertical blanking interval */ 781 num = (mode->hdisplay - 25) * link_rate; 782 config->vblank_symbols = div_u64(num, pclk); 783 config->vblank_symbols -= 36 / link->num_lanes + 4; 784 785 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 786 config->vblank_symbols); 787 788 return 0; 789 } 790 791 static void tegra_sor_apply_config(struct tegra_sor *sor, 792 const struct tegra_sor_config *config) 793 { 794 u32 value; 795 796 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 797 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 798 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); 799 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 800 801 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); 802 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 803 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); 804 805 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 806 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); 807 808 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 809 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); 810 811 if (config->active_polarity) 812 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 813 else 814 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 815 816 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 817 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 818 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); 819 820 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 821 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 822 value |= config->hblank_symbols & 0xffff; 823 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 824 825 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 826 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 827 value |= config->vblank_symbols & 0xffff; 828 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 829 } 830 831 static void tegra_sor_mode_set(struct tegra_sor *sor, 832 const struct drm_display_mode *mode, 833 struct tegra_sor_state *state) 834 { 835 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 836 unsigned int vbe, vse, hbe, hse, vbs, hbs; 837 u32 value; 838 839 value = tegra_sor_readl(sor, SOR_STATE1); 840 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; 841 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 842 value &= ~SOR_STATE_ASY_OWNER_MASK; 843 844 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | 845 SOR_STATE_ASY_OWNER(dc->pipe + 1); 846 847 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 848 value &= ~SOR_STATE_ASY_HSYNCPOL; 849 850 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 851 value |= SOR_STATE_ASY_HSYNCPOL; 852 853 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 854 value &= ~SOR_STATE_ASY_VSYNCPOL; 855 856 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 857 value |= SOR_STATE_ASY_VSYNCPOL; 858 859 switch (state->bpc) { 860 case 16: 861 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; 862 break; 863 864 case 12: 865 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; 866 break; 867 868 case 10: 869 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; 870 break; 871 872 case 8: 873 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 874 break; 875 876 case 6: 877 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 878 break; 879 880 default: 881 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 882 break; 883 } 884 885 tegra_sor_writel(sor, value, SOR_STATE1); 886 887 /* 888 * TODO: The video timing programming below doesn't seem to match the 889 * register definitions. 890 */ 891 892 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 893 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); 894 895 /* sync end = sync width - 1 */ 896 vse = mode->vsync_end - mode->vsync_start - 1; 897 hse = mode->hsync_end - mode->hsync_start - 1; 898 899 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 900 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); 901 902 /* blank end = sync end + back porch */ 903 vbe = vse + (mode->vtotal - mode->vsync_end); 904 hbe = hse + (mode->htotal - mode->hsync_end); 905 906 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 907 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); 908 909 /* blank start = blank end + active */ 910 vbs = vbe + mode->vdisplay; 911 hbs = hbe + mode->hdisplay; 912 913 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 914 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); 915 916 /* XXX interlacing support */ 917 tegra_sor_writel(sor, 0x001, SOR_HEAD_STATE5(dc->pipe)); 918 } 919 920 static int tegra_sor_detach(struct tegra_sor *sor) 921 { 922 unsigned long value, timeout; 923 924 /* switch to safe mode */ 925 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 926 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 927 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 928 tegra_sor_super_update(sor); 929 930 timeout = jiffies + msecs_to_jiffies(250); 931 932 while (time_before(jiffies, timeout)) { 933 value = tegra_sor_readl(sor, SOR_PWR); 934 if (value & SOR_PWR_MODE_SAFE) 935 break; 936 } 937 938 if ((value & SOR_PWR_MODE_SAFE) == 0) 939 return -ETIMEDOUT; 940 941 /* go to sleep */ 942 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 943 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 944 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 945 tegra_sor_super_update(sor); 946 947 /* detach */ 948 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 949 value &= ~SOR_SUPER_STATE_ATTACHED; 950 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 951 tegra_sor_super_update(sor); 952 953 timeout = jiffies + msecs_to_jiffies(250); 954 955 while (time_before(jiffies, timeout)) { 956 value = tegra_sor_readl(sor, SOR_TEST); 957 if ((value & SOR_TEST_ATTACHED) == 0) 958 break; 959 960 usleep_range(25, 100); 961 } 962 963 if ((value & SOR_TEST_ATTACHED) != 0) 964 return -ETIMEDOUT; 965 966 return 0; 967 } 968 969 static int tegra_sor_power_down(struct tegra_sor *sor) 970 { 971 unsigned long value, timeout; 972 int err; 973 974 value = tegra_sor_readl(sor, SOR_PWR); 975 value &= ~SOR_PWR_NORMAL_STATE_PU; 976 value |= SOR_PWR_TRIGGER; 977 tegra_sor_writel(sor, value, SOR_PWR); 978 979 timeout = jiffies + msecs_to_jiffies(250); 980 981 while (time_before(jiffies, timeout)) { 982 value = tegra_sor_readl(sor, SOR_PWR); 983 if ((value & SOR_PWR_TRIGGER) == 0) 984 return 0; 985 986 usleep_range(25, 100); 987 } 988 989 if ((value & SOR_PWR_TRIGGER) != 0) 990 return -ETIMEDOUT; 991 992 /* switch to safe parent clock */ 993 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 994 if (err < 0) 995 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 996 997 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 998 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 999 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 1000 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1001 1002 /* stop lane sequencer */ 1003 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 1004 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 1005 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 1006 1007 timeout = jiffies + msecs_to_jiffies(250); 1008 1009 while (time_before(jiffies, timeout)) { 1010 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 1011 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 1012 break; 1013 1014 usleep_range(25, 100); 1015 } 1016 1017 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 1018 return -ETIMEDOUT; 1019 1020 value = tegra_sor_readl(sor, SOR_PLL2); 1021 value |= SOR_PLL2_PORT_POWERDOWN; 1022 tegra_sor_writel(sor, value, SOR_PLL2); 1023 1024 usleep_range(20, 100); 1025 1026 value = tegra_sor_readl(sor, SOR_PLL0); 1027 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1028 tegra_sor_writel(sor, value, SOR_PLL0); 1029 1030 value = tegra_sor_readl(sor, SOR_PLL2); 1031 value |= SOR_PLL2_SEQ_PLLCAPPD; 1032 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1033 tegra_sor_writel(sor, value, SOR_PLL2); 1034 1035 usleep_range(20, 100); 1036 1037 return 0; 1038 } 1039 1040 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 1041 { 1042 u32 value; 1043 1044 timeout = jiffies + msecs_to_jiffies(timeout); 1045 1046 while (time_before(jiffies, timeout)) { 1047 value = tegra_sor_readl(sor, SOR_CRCA); 1048 if (value & SOR_CRCA_VALID) 1049 return 0; 1050 1051 usleep_range(100, 200); 1052 } 1053 1054 return -ETIMEDOUT; 1055 } 1056 1057 static int tegra_sor_show_crc(struct seq_file *s, void *data) 1058 { 1059 struct drm_info_node *node = s->private; 1060 struct tegra_sor *sor = node->info_ent->data; 1061 struct drm_crtc *crtc = sor->output.encoder.crtc; 1062 struct drm_device *drm = node->minor->dev; 1063 int err = 0; 1064 u32 value; 1065 1066 drm_modeset_lock_all(drm); 1067 1068 if (!crtc || !crtc->state->active) { 1069 err = -EBUSY; 1070 goto unlock; 1071 } 1072 1073 value = tegra_sor_readl(sor, SOR_STATE1); 1074 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1075 tegra_sor_writel(sor, value, SOR_STATE1); 1076 1077 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 1078 value |= SOR_CRC_CNTRL_ENABLE; 1079 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 1080 1081 value = tegra_sor_readl(sor, SOR_TEST); 1082 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 1083 tegra_sor_writel(sor, value, SOR_TEST); 1084 1085 err = tegra_sor_crc_wait(sor, 100); 1086 if (err < 0) 1087 goto unlock; 1088 1089 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); 1090 value = tegra_sor_readl(sor, SOR_CRCB); 1091 1092 seq_printf(s, "%08x\n", value); 1093 1094 unlock: 1095 drm_modeset_unlock_all(drm); 1096 return err; 1097 } 1098 1099 static int tegra_sor_show_regs(struct seq_file *s, void *data) 1100 { 1101 struct drm_info_node *node = s->private; 1102 struct tegra_sor *sor = node->info_ent->data; 1103 struct drm_crtc *crtc = sor->output.encoder.crtc; 1104 struct drm_device *drm = node->minor->dev; 1105 int err = 0; 1106 1107 drm_modeset_lock_all(drm); 1108 1109 if (!crtc || !crtc->state->active) { 1110 err = -EBUSY; 1111 goto unlock; 1112 } 1113 1114 #define DUMP_REG(name) \ 1115 seq_printf(s, "%-38s %#05x %08x\n", #name, name, \ 1116 tegra_sor_readl(sor, name)) 1117 1118 DUMP_REG(SOR_CTXSW); 1119 DUMP_REG(SOR_SUPER_STATE0); 1120 DUMP_REG(SOR_SUPER_STATE1); 1121 DUMP_REG(SOR_STATE0); 1122 DUMP_REG(SOR_STATE1); 1123 DUMP_REG(SOR_HEAD_STATE0(0)); 1124 DUMP_REG(SOR_HEAD_STATE0(1)); 1125 DUMP_REG(SOR_HEAD_STATE1(0)); 1126 DUMP_REG(SOR_HEAD_STATE1(1)); 1127 DUMP_REG(SOR_HEAD_STATE2(0)); 1128 DUMP_REG(SOR_HEAD_STATE2(1)); 1129 DUMP_REG(SOR_HEAD_STATE3(0)); 1130 DUMP_REG(SOR_HEAD_STATE3(1)); 1131 DUMP_REG(SOR_HEAD_STATE4(0)); 1132 DUMP_REG(SOR_HEAD_STATE4(1)); 1133 DUMP_REG(SOR_HEAD_STATE5(0)); 1134 DUMP_REG(SOR_HEAD_STATE5(1)); 1135 DUMP_REG(SOR_CRC_CNTRL); 1136 DUMP_REG(SOR_DP_DEBUG_MVID); 1137 DUMP_REG(SOR_CLK_CNTRL); 1138 DUMP_REG(SOR_CAP); 1139 DUMP_REG(SOR_PWR); 1140 DUMP_REG(SOR_TEST); 1141 DUMP_REG(SOR_PLL0); 1142 DUMP_REG(SOR_PLL1); 1143 DUMP_REG(SOR_PLL2); 1144 DUMP_REG(SOR_PLL3); 1145 DUMP_REG(SOR_CSTM); 1146 DUMP_REG(SOR_LVDS); 1147 DUMP_REG(SOR_CRCA); 1148 DUMP_REG(SOR_CRCB); 1149 DUMP_REG(SOR_BLANK); 1150 DUMP_REG(SOR_SEQ_CTL); 1151 DUMP_REG(SOR_LANE_SEQ_CTL); 1152 DUMP_REG(SOR_SEQ_INST(0)); 1153 DUMP_REG(SOR_SEQ_INST(1)); 1154 DUMP_REG(SOR_SEQ_INST(2)); 1155 DUMP_REG(SOR_SEQ_INST(3)); 1156 DUMP_REG(SOR_SEQ_INST(4)); 1157 DUMP_REG(SOR_SEQ_INST(5)); 1158 DUMP_REG(SOR_SEQ_INST(6)); 1159 DUMP_REG(SOR_SEQ_INST(7)); 1160 DUMP_REG(SOR_SEQ_INST(8)); 1161 DUMP_REG(SOR_SEQ_INST(9)); 1162 DUMP_REG(SOR_SEQ_INST(10)); 1163 DUMP_REG(SOR_SEQ_INST(11)); 1164 DUMP_REG(SOR_SEQ_INST(12)); 1165 DUMP_REG(SOR_SEQ_INST(13)); 1166 DUMP_REG(SOR_SEQ_INST(14)); 1167 DUMP_REG(SOR_SEQ_INST(15)); 1168 DUMP_REG(SOR_PWM_DIV); 1169 DUMP_REG(SOR_PWM_CTL); 1170 DUMP_REG(SOR_VCRC_A0); 1171 DUMP_REG(SOR_VCRC_A1); 1172 DUMP_REG(SOR_VCRC_B0); 1173 DUMP_REG(SOR_VCRC_B1); 1174 DUMP_REG(SOR_CCRC_A0); 1175 DUMP_REG(SOR_CCRC_A1); 1176 DUMP_REG(SOR_CCRC_B0); 1177 DUMP_REG(SOR_CCRC_B1); 1178 DUMP_REG(SOR_EDATA_A0); 1179 DUMP_REG(SOR_EDATA_A1); 1180 DUMP_REG(SOR_EDATA_B0); 1181 DUMP_REG(SOR_EDATA_B1); 1182 DUMP_REG(SOR_COUNT_A0); 1183 DUMP_REG(SOR_COUNT_A1); 1184 DUMP_REG(SOR_COUNT_B0); 1185 DUMP_REG(SOR_COUNT_B1); 1186 DUMP_REG(SOR_DEBUG_A0); 1187 DUMP_REG(SOR_DEBUG_A1); 1188 DUMP_REG(SOR_DEBUG_B0); 1189 DUMP_REG(SOR_DEBUG_B1); 1190 DUMP_REG(SOR_TRIG); 1191 DUMP_REG(SOR_MSCHECK); 1192 DUMP_REG(SOR_XBAR_CTRL); 1193 DUMP_REG(SOR_XBAR_POL); 1194 DUMP_REG(SOR_DP_LINKCTL0); 1195 DUMP_REG(SOR_DP_LINKCTL1); 1196 DUMP_REG(SOR_LANE_DRIVE_CURRENT0); 1197 DUMP_REG(SOR_LANE_DRIVE_CURRENT1); 1198 DUMP_REG(SOR_LANE4_DRIVE_CURRENT0); 1199 DUMP_REG(SOR_LANE4_DRIVE_CURRENT1); 1200 DUMP_REG(SOR_LANE_PREEMPHASIS0); 1201 DUMP_REG(SOR_LANE_PREEMPHASIS1); 1202 DUMP_REG(SOR_LANE4_PREEMPHASIS0); 1203 DUMP_REG(SOR_LANE4_PREEMPHASIS1); 1204 DUMP_REG(SOR_LANE_POSTCURSOR0); 1205 DUMP_REG(SOR_LANE_POSTCURSOR1); 1206 DUMP_REG(SOR_DP_CONFIG0); 1207 DUMP_REG(SOR_DP_CONFIG1); 1208 DUMP_REG(SOR_DP_MN0); 1209 DUMP_REG(SOR_DP_MN1); 1210 DUMP_REG(SOR_DP_PADCTL0); 1211 DUMP_REG(SOR_DP_PADCTL1); 1212 DUMP_REG(SOR_DP_DEBUG0); 1213 DUMP_REG(SOR_DP_DEBUG1); 1214 DUMP_REG(SOR_DP_SPARE0); 1215 DUMP_REG(SOR_DP_SPARE1); 1216 DUMP_REG(SOR_DP_AUDIO_CTRL); 1217 DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS); 1218 DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS); 1219 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER); 1220 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0); 1221 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1); 1222 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2); 1223 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3); 1224 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4); 1225 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5); 1226 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6); 1227 DUMP_REG(SOR_DP_TPG); 1228 DUMP_REG(SOR_DP_TPG_CONFIG); 1229 DUMP_REG(SOR_DP_LQ_CSTM0); 1230 DUMP_REG(SOR_DP_LQ_CSTM1); 1231 DUMP_REG(SOR_DP_LQ_CSTM2); 1232 1233 #undef DUMP_REG 1234 1235 unlock: 1236 drm_modeset_unlock_all(drm); 1237 return err; 1238 } 1239 1240 static const struct drm_info_list debugfs_files[] = { 1241 { "crc", tegra_sor_show_crc, 0, NULL }, 1242 { "regs", tegra_sor_show_regs, 0, NULL }, 1243 }; 1244 1245 static int tegra_sor_debugfs_init(struct tegra_sor *sor, 1246 struct drm_minor *minor) 1247 { 1248 const char *name = sor->soc->supports_dp ? "sor1" : "sor"; 1249 unsigned int i; 1250 int err; 1251 1252 sor->debugfs = debugfs_create_dir(name, minor->debugfs_root); 1253 if (!sor->debugfs) 1254 return -ENOMEM; 1255 1256 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1257 GFP_KERNEL); 1258 if (!sor->debugfs_files) { 1259 err = -ENOMEM; 1260 goto remove; 1261 } 1262 1263 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) 1264 sor->debugfs_files[i].data = sor; 1265 1266 err = drm_debugfs_create_files(sor->debugfs_files, 1267 ARRAY_SIZE(debugfs_files), 1268 sor->debugfs, minor); 1269 if (err < 0) 1270 goto free; 1271 1272 sor->minor = minor; 1273 1274 return 0; 1275 1276 free: 1277 kfree(sor->debugfs_files); 1278 sor->debugfs_files = NULL; 1279 remove: 1280 debugfs_remove_recursive(sor->debugfs); 1281 sor->debugfs = NULL; 1282 return err; 1283 } 1284 1285 static void tegra_sor_debugfs_exit(struct tegra_sor *sor) 1286 { 1287 drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files), 1288 sor->minor); 1289 sor->minor = NULL; 1290 1291 kfree(sor->debugfs_files); 1292 sor->debugfs_files = NULL; 1293 1294 debugfs_remove_recursive(sor->debugfs); 1295 sor->debugfs = NULL; 1296 } 1297 1298 static void tegra_sor_connector_reset(struct drm_connector *connector) 1299 { 1300 struct tegra_sor_state *state; 1301 1302 state = kzalloc(sizeof(*state), GFP_KERNEL); 1303 if (!state) 1304 return; 1305 1306 if (connector->state) { 1307 __drm_atomic_helper_connector_destroy_state(connector->state); 1308 kfree(connector->state); 1309 } 1310 1311 __drm_atomic_helper_connector_reset(connector, &state->base); 1312 } 1313 1314 static enum drm_connector_status 1315 tegra_sor_connector_detect(struct drm_connector *connector, bool force) 1316 { 1317 struct tegra_output *output = connector_to_output(connector); 1318 struct tegra_sor *sor = to_sor(output); 1319 1320 if (sor->aux) 1321 return drm_dp_aux_detect(sor->aux); 1322 1323 return tegra_output_connector_detect(connector, force); 1324 } 1325 1326 static struct drm_connector_state * 1327 tegra_sor_connector_duplicate_state(struct drm_connector *connector) 1328 { 1329 struct tegra_sor_state *state = to_sor_state(connector->state); 1330 struct tegra_sor_state *copy; 1331 1332 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 1333 if (!copy) 1334 return NULL; 1335 1336 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); 1337 1338 return ©->base; 1339 } 1340 1341 static const struct drm_connector_funcs tegra_sor_connector_funcs = { 1342 .dpms = drm_atomic_helper_connector_dpms, 1343 .reset = tegra_sor_connector_reset, 1344 .detect = tegra_sor_connector_detect, 1345 .fill_modes = drm_helper_probe_single_connector_modes, 1346 .destroy = tegra_output_connector_destroy, 1347 .atomic_duplicate_state = tegra_sor_connector_duplicate_state, 1348 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1349 }; 1350 1351 static int tegra_sor_connector_get_modes(struct drm_connector *connector) 1352 { 1353 struct tegra_output *output = connector_to_output(connector); 1354 struct tegra_sor *sor = to_sor(output); 1355 int err; 1356 1357 if (sor->aux) 1358 drm_dp_aux_enable(sor->aux); 1359 1360 err = tegra_output_connector_get_modes(connector); 1361 1362 if (sor->aux) 1363 drm_dp_aux_disable(sor->aux); 1364 1365 return err; 1366 } 1367 1368 static enum drm_mode_status 1369 tegra_sor_connector_mode_valid(struct drm_connector *connector, 1370 struct drm_display_mode *mode) 1371 { 1372 return MODE_OK; 1373 } 1374 1375 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { 1376 .get_modes = tegra_sor_connector_get_modes, 1377 .mode_valid = tegra_sor_connector_mode_valid, 1378 .best_encoder = tegra_output_connector_best_encoder, 1379 }; 1380 1381 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { 1382 .destroy = tegra_output_encoder_destroy, 1383 }; 1384 1385 static void tegra_sor_edp_disable(struct drm_encoder *encoder) 1386 { 1387 struct tegra_output *output = encoder_to_output(encoder); 1388 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1389 struct tegra_sor *sor = to_sor(output); 1390 u32 value; 1391 int err; 1392 1393 if (output->panel) 1394 drm_panel_disable(output->panel); 1395 1396 err = tegra_sor_detach(sor); 1397 if (err < 0) 1398 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1399 1400 tegra_sor_writel(sor, 0, SOR_STATE1); 1401 tegra_sor_update(sor); 1402 1403 /* 1404 * The following accesses registers of the display controller, so make 1405 * sure it's only executed when the output is attached to one. 1406 */ 1407 if (dc) { 1408 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1409 value &= ~SOR_ENABLE; 1410 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1411 1412 tegra_dc_commit(dc); 1413 } 1414 1415 err = tegra_sor_power_down(sor); 1416 if (err < 0) 1417 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1418 1419 if (sor->aux) { 1420 err = drm_dp_aux_disable(sor->aux); 1421 if (err < 0) 1422 dev_err(sor->dev, "failed to disable DP: %d\n", err); 1423 } 1424 1425 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); 1426 if (err < 0) 1427 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); 1428 1429 if (output->panel) 1430 drm_panel_unprepare(output->panel); 1431 1432 pm_runtime_put(sor->dev); 1433 } 1434 1435 #if 0 1436 static int calc_h_ref_to_sync(const struct drm_display_mode *mode, 1437 unsigned int *value) 1438 { 1439 unsigned int hfp, hsw, hbp, a = 0, b; 1440 1441 hfp = mode->hsync_start - mode->hdisplay; 1442 hsw = mode->hsync_end - mode->hsync_start; 1443 hbp = mode->htotal - mode->hsync_end; 1444 1445 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp); 1446 1447 b = hfp - 1; 1448 1449 pr_info("a: %u, b: %u\n", a, b); 1450 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp); 1451 1452 if (a + hsw + hbp <= 11) { 1453 a = 1 + 11 - hsw - hbp; 1454 pr_info("a: %u\n", a); 1455 } 1456 1457 if (a > b) 1458 return -EINVAL; 1459 1460 if (hsw < 1) 1461 return -EINVAL; 1462 1463 if (mode->hdisplay < 16) 1464 return -EINVAL; 1465 1466 if (value) { 1467 if (b > a && a % 2) 1468 *value = a + 1; 1469 else 1470 *value = a; 1471 } 1472 1473 return 0; 1474 } 1475 #endif 1476 1477 static void tegra_sor_edp_enable(struct drm_encoder *encoder) 1478 { 1479 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 1480 struct tegra_output *output = encoder_to_output(encoder); 1481 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1482 struct tegra_sor *sor = to_sor(output); 1483 struct tegra_sor_config config; 1484 struct tegra_sor_state *state; 1485 struct drm_dp_link link; 1486 u8 rate, lanes; 1487 unsigned int i; 1488 int err = 0; 1489 u32 value; 1490 1491 state = to_sor_state(output->connector.state); 1492 1493 pm_runtime_get_sync(sor->dev); 1494 1495 if (output->panel) 1496 drm_panel_prepare(output->panel); 1497 1498 err = drm_dp_aux_enable(sor->aux); 1499 if (err < 0) 1500 dev_err(sor->dev, "failed to enable DP: %d\n", err); 1501 1502 err = drm_dp_link_probe(sor->aux, &link); 1503 if (err < 0) { 1504 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 1505 return; 1506 } 1507 1508 /* switch to safe parent clock */ 1509 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1510 if (err < 0) 1511 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1512 1513 memset(&config, 0, sizeof(config)); 1514 config.bits_per_pixel = state->bpc * 3; 1515 1516 err = tegra_sor_compute_config(sor, mode, &config, &link); 1517 if (err < 0) 1518 dev_err(sor->dev, "failed to compute configuration: %d\n", err); 1519 1520 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1521 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 1522 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 1523 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1524 1525 value = tegra_sor_readl(sor, SOR_PLL2); 1526 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1527 tegra_sor_writel(sor, value, SOR_PLL2); 1528 usleep_range(20, 100); 1529 1530 value = tegra_sor_readl(sor, SOR_PLL3); 1531 value |= SOR_PLL3_PLL_VDD_MODE_3V3; 1532 tegra_sor_writel(sor, value, SOR_PLL3); 1533 1534 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | 1535 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; 1536 tegra_sor_writel(sor, value, SOR_PLL0); 1537 1538 value = tegra_sor_readl(sor, SOR_PLL2); 1539 value |= SOR_PLL2_SEQ_PLLCAPPD; 1540 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1541 value |= SOR_PLL2_LVDS_ENABLE; 1542 tegra_sor_writel(sor, value, SOR_PLL2); 1543 1544 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; 1545 tegra_sor_writel(sor, value, SOR_PLL1); 1546 1547 while (true) { 1548 value = tegra_sor_readl(sor, SOR_PLL2); 1549 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) 1550 break; 1551 1552 usleep_range(250, 1000); 1553 } 1554 1555 value = tegra_sor_readl(sor, SOR_PLL2); 1556 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 1557 value &= ~SOR_PLL2_PORT_POWERDOWN; 1558 tegra_sor_writel(sor, value, SOR_PLL2); 1559 1560 /* 1561 * power up 1562 */ 1563 1564 /* set safe link bandwidth (1.62 Gbps) */ 1565 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1566 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1567 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; 1568 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1569 1570 /* step 1 */ 1571 value = tegra_sor_readl(sor, SOR_PLL2); 1572 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | 1573 SOR_PLL2_BANDGAP_POWERDOWN; 1574 tegra_sor_writel(sor, value, SOR_PLL2); 1575 1576 value = tegra_sor_readl(sor, SOR_PLL0); 1577 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1578 tegra_sor_writel(sor, value, SOR_PLL0); 1579 1580 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1581 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 1582 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1583 1584 /* step 2 */ 1585 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); 1586 if (err < 0) 1587 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); 1588 1589 usleep_range(5, 100); 1590 1591 /* step 3 */ 1592 value = tegra_sor_readl(sor, SOR_PLL2); 1593 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1594 tegra_sor_writel(sor, value, SOR_PLL2); 1595 1596 usleep_range(20, 100); 1597 1598 /* step 4 */ 1599 value = tegra_sor_readl(sor, SOR_PLL0); 1600 value &= ~SOR_PLL0_VCOPD; 1601 value &= ~SOR_PLL0_PWR; 1602 tegra_sor_writel(sor, value, SOR_PLL0); 1603 1604 value = tegra_sor_readl(sor, SOR_PLL2); 1605 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1606 tegra_sor_writel(sor, value, SOR_PLL2); 1607 1608 usleep_range(200, 1000); 1609 1610 /* step 5 */ 1611 value = tegra_sor_readl(sor, SOR_PLL2); 1612 value &= ~SOR_PLL2_PORT_POWERDOWN; 1613 tegra_sor_writel(sor, value, SOR_PLL2); 1614 1615 /* switch to DP parent clock */ 1616 err = tegra_sor_set_parent_clock(sor, sor->clk_dp); 1617 if (err < 0) 1618 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 1619 1620 /* power DP lanes */ 1621 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1622 1623 if (link.num_lanes <= 2) 1624 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); 1625 else 1626 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; 1627 1628 if (link.num_lanes <= 1) 1629 value &= ~SOR_DP_PADCTL_PD_TXD_1; 1630 else 1631 value |= SOR_DP_PADCTL_PD_TXD_1; 1632 1633 if (link.num_lanes == 0) 1634 value &= ~SOR_DP_PADCTL_PD_TXD_0; 1635 else 1636 value |= SOR_DP_PADCTL_PD_TXD_0; 1637 1638 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1639 1640 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1641 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1642 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); 1643 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1644 1645 /* start lane sequencer */ 1646 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 1647 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 1648 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 1649 1650 while (true) { 1651 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 1652 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 1653 break; 1654 1655 usleep_range(250, 1000); 1656 } 1657 1658 /* set link bandwidth */ 1659 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1660 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1661 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; 1662 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1663 1664 tegra_sor_apply_config(sor, &config); 1665 1666 /* enable link */ 1667 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1668 value |= SOR_DP_LINKCTL_ENABLE; 1669 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 1670 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1671 1672 for (i = 0, value = 0; i < 4; i++) { 1673 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 1674 SOR_DP_TPG_SCRAMBLER_GALIOS | 1675 SOR_DP_TPG_PATTERN_NONE; 1676 value = (value << 8) | lane; 1677 } 1678 1679 tegra_sor_writel(sor, value, SOR_DP_TPG); 1680 1681 /* enable pad calibration logic */ 1682 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1683 value |= SOR_DP_PADCTL_PAD_CAL_PD; 1684 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1685 1686 err = drm_dp_link_probe(sor->aux, &link); 1687 if (err < 0) 1688 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 1689 1690 err = drm_dp_link_power_up(sor->aux, &link); 1691 if (err < 0) 1692 dev_err(sor->dev, "failed to power up eDP link: %d\n", err); 1693 1694 err = drm_dp_link_configure(sor->aux, &link); 1695 if (err < 0) 1696 dev_err(sor->dev, "failed to configure eDP link: %d\n", err); 1697 1698 rate = drm_dp_link_rate_to_bw_code(link.rate); 1699 lanes = link.num_lanes; 1700 1701 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1702 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1703 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 1704 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1705 1706 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1707 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1708 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 1709 1710 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1711 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 1712 1713 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1714 1715 /* disable training pattern generator */ 1716 1717 for (i = 0; i < link.num_lanes; i++) { 1718 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 1719 SOR_DP_TPG_SCRAMBLER_GALIOS | 1720 SOR_DP_TPG_PATTERN_NONE; 1721 value = (value << 8) | lane; 1722 } 1723 1724 tegra_sor_writel(sor, value, SOR_DP_TPG); 1725 1726 err = tegra_sor_dp_train_fast(sor, &link); 1727 if (err < 0) 1728 dev_err(sor->dev, "DP fast link training failed: %d\n", err); 1729 1730 dev_dbg(sor->dev, "fast link training succeeded\n"); 1731 1732 err = tegra_sor_power_up(sor, 250); 1733 if (err < 0) 1734 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 1735 1736 /* CSTM (LVDS, link A/B, upper) */ 1737 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 1738 SOR_CSTM_UPPER; 1739 tegra_sor_writel(sor, value, SOR_CSTM); 1740 1741 /* use DP-A protocol */ 1742 value = tegra_sor_readl(sor, SOR_STATE1); 1743 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 1744 value |= SOR_STATE_ASY_PROTOCOL_DP_A; 1745 tegra_sor_writel(sor, value, SOR_STATE1); 1746 1747 tegra_sor_mode_set(sor, mode, state); 1748 1749 /* PWM setup */ 1750 err = tegra_sor_setup_pwm(sor, 250); 1751 if (err < 0) 1752 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 1753 1754 tegra_sor_update(sor); 1755 1756 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1757 value |= SOR_ENABLE; 1758 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1759 1760 tegra_dc_commit(dc); 1761 1762 err = tegra_sor_attach(sor); 1763 if (err < 0) 1764 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 1765 1766 err = tegra_sor_wakeup(sor); 1767 if (err < 0) 1768 dev_err(sor->dev, "failed to enable DC: %d\n", err); 1769 1770 if (output->panel) 1771 drm_panel_enable(output->panel); 1772 } 1773 1774 static int 1775 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, 1776 struct drm_crtc_state *crtc_state, 1777 struct drm_connector_state *conn_state) 1778 { 1779 struct tegra_output *output = encoder_to_output(encoder); 1780 struct tegra_sor_state *state = to_sor_state(conn_state); 1781 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 1782 unsigned long pclk = crtc_state->mode.clock * 1000; 1783 struct tegra_sor *sor = to_sor(output); 1784 struct drm_display_info *info; 1785 int err; 1786 1787 info = &output->connector.display_info; 1788 1789 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, 1790 pclk, 0); 1791 if (err < 0) { 1792 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1793 return err; 1794 } 1795 1796 switch (info->bpc) { 1797 case 8: 1798 case 6: 1799 state->bpc = info->bpc; 1800 break; 1801 1802 default: 1803 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); 1804 state->bpc = 8; 1805 break; 1806 } 1807 1808 return 0; 1809 } 1810 1811 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = { 1812 .disable = tegra_sor_edp_disable, 1813 .enable = tegra_sor_edp_enable, 1814 .atomic_check = tegra_sor_encoder_atomic_check, 1815 }; 1816 1817 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) 1818 { 1819 u32 value = 0; 1820 size_t i; 1821 1822 for (i = size; i > 0; i--) 1823 value = (value << 8) | ptr[i - 1]; 1824 1825 return value; 1826 } 1827 1828 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, 1829 const void *data, size_t size) 1830 { 1831 const u8 *ptr = data; 1832 unsigned long offset; 1833 size_t i, j; 1834 u32 value; 1835 1836 switch (ptr[0]) { 1837 case HDMI_INFOFRAME_TYPE_AVI: 1838 offset = SOR_HDMI_AVI_INFOFRAME_HEADER; 1839 break; 1840 1841 case HDMI_INFOFRAME_TYPE_AUDIO: 1842 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; 1843 break; 1844 1845 case HDMI_INFOFRAME_TYPE_VENDOR: 1846 offset = SOR_HDMI_VSI_INFOFRAME_HEADER; 1847 break; 1848 1849 default: 1850 dev_err(sor->dev, "unsupported infoframe type: %02x\n", 1851 ptr[0]); 1852 return; 1853 } 1854 1855 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 1856 INFOFRAME_HEADER_VERSION(ptr[1]) | 1857 INFOFRAME_HEADER_LEN(ptr[2]); 1858 tegra_sor_writel(sor, value, offset); 1859 offset++; 1860 1861 /* 1862 * Each subpack contains 7 bytes, divided into: 1863 * - subpack_low: bytes 0 - 3 1864 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 1865 */ 1866 for (i = 3, j = 0; i < size; i += 7, j += 8) { 1867 size_t rem = size - i, num = min_t(size_t, rem, 4); 1868 1869 value = tegra_sor_hdmi_subpack(&ptr[i], num); 1870 tegra_sor_writel(sor, value, offset++); 1871 1872 num = min_t(size_t, rem - num, 3); 1873 1874 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); 1875 tegra_sor_writel(sor, value, offset++); 1876 } 1877 } 1878 1879 static int 1880 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, 1881 const struct drm_display_mode *mode) 1882 { 1883 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 1884 struct hdmi_avi_infoframe frame; 1885 u32 value; 1886 int err; 1887 1888 /* disable AVI infoframe */ 1889 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 1890 value &= ~INFOFRAME_CTRL_SINGLE; 1891 value &= ~INFOFRAME_CTRL_OTHER; 1892 value &= ~INFOFRAME_CTRL_ENABLE; 1893 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 1894 1895 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1896 if (err < 0) { 1897 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 1898 return err; 1899 } 1900 1901 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1902 if (err < 0) { 1903 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); 1904 return err; 1905 } 1906 1907 tegra_sor_hdmi_write_infopack(sor, buffer, err); 1908 1909 /* enable AVI infoframe */ 1910 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 1911 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 1912 value |= INFOFRAME_CTRL_ENABLE; 1913 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 1914 1915 return 0; 1916 } 1917 1918 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) 1919 { 1920 u32 value; 1921 1922 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 1923 value &= ~INFOFRAME_CTRL_ENABLE; 1924 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 1925 } 1926 1927 static struct tegra_sor_hdmi_settings * 1928 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) 1929 { 1930 unsigned int i; 1931 1932 for (i = 0; i < sor->num_settings; i++) 1933 if (frequency <= sor->settings[i].frequency) 1934 return &sor->settings[i]; 1935 1936 return NULL; 1937 } 1938 1939 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) 1940 { 1941 struct tegra_output *output = encoder_to_output(encoder); 1942 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1943 struct tegra_sor *sor = to_sor(output); 1944 u32 value; 1945 int err; 1946 1947 err = tegra_sor_detach(sor); 1948 if (err < 0) 1949 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1950 1951 tegra_sor_writel(sor, 0, SOR_STATE1); 1952 tegra_sor_update(sor); 1953 1954 /* disable display to SOR clock */ 1955 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1956 value &= ~SOR1_TIMING_CYA; 1957 value &= ~SOR1_ENABLE; 1958 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1959 1960 tegra_dc_commit(dc); 1961 1962 err = tegra_sor_power_down(sor); 1963 if (err < 0) 1964 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1965 1966 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI); 1967 if (err < 0) 1968 dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err); 1969 1970 pm_runtime_put(sor->dev); 1971 } 1972 1973 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) 1974 { 1975 struct tegra_output *output = encoder_to_output(encoder); 1976 unsigned int h_ref_to_sync = 1, pulse_start, max_ac; 1977 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1978 struct tegra_sor_hdmi_settings *settings; 1979 struct tegra_sor *sor = to_sor(output); 1980 struct tegra_sor_state *state; 1981 struct drm_display_mode *mode; 1982 unsigned int div; 1983 u32 value; 1984 int err; 1985 1986 state = to_sor_state(output->connector.state); 1987 mode = &encoder->crtc->state->adjusted_mode; 1988 1989 pm_runtime_get_sync(sor->dev); 1990 1991 /* switch to safe parent clock */ 1992 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1993 if (err < 0) 1994 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1995 1996 div = clk_get_rate(sor->clk) / 1000000 * 4; 1997 1998 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI); 1999 if (err < 0) 2000 dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err); 2001 2002 usleep_range(20, 100); 2003 2004 value = tegra_sor_readl(sor, SOR_PLL2); 2005 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2006 tegra_sor_writel(sor, value, SOR_PLL2); 2007 2008 usleep_range(20, 100); 2009 2010 value = tegra_sor_readl(sor, SOR_PLL3); 2011 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; 2012 tegra_sor_writel(sor, value, SOR_PLL3); 2013 2014 value = tegra_sor_readl(sor, SOR_PLL0); 2015 value &= ~SOR_PLL0_VCOPD; 2016 value &= ~SOR_PLL0_PWR; 2017 tegra_sor_writel(sor, value, SOR_PLL0); 2018 2019 value = tegra_sor_readl(sor, SOR_PLL2); 2020 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2021 tegra_sor_writel(sor, value, SOR_PLL2); 2022 2023 usleep_range(200, 400); 2024 2025 value = tegra_sor_readl(sor, SOR_PLL2); 2026 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2027 value &= ~SOR_PLL2_PORT_POWERDOWN; 2028 tegra_sor_writel(sor, value, SOR_PLL2); 2029 2030 usleep_range(20, 100); 2031 2032 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2033 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 2034 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 2035 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2036 2037 while (true) { 2038 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2039 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) 2040 break; 2041 2042 usleep_range(250, 1000); 2043 } 2044 2045 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 2046 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); 2047 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 2048 2049 while (true) { 2050 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2051 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 2052 break; 2053 2054 usleep_range(250, 1000); 2055 } 2056 2057 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2058 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 2059 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2060 2061 if (mode->clock < 340000) 2062 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 2063 else 2064 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; 2065 2066 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 2067 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2068 2069 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2070 value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2071 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2072 value |= SOR_DP_SPARE_SEQ_ENABLE; 2073 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2074 2075 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | 2076 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); 2077 tegra_sor_writel(sor, value, SOR_SEQ_CTL); 2078 2079 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | 2080 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); 2081 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); 2082 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); 2083 2084 /* program the reference clock */ 2085 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); 2086 tegra_sor_writel(sor, value, SOR_REFCLK); 2087 2088 /* XXX don't hardcode */ 2089 value = SOR_XBAR_CTRL_LINK1_XSEL(4, 4) | 2090 SOR_XBAR_CTRL_LINK1_XSEL(3, 3) | 2091 SOR_XBAR_CTRL_LINK1_XSEL(2, 2) | 2092 SOR_XBAR_CTRL_LINK1_XSEL(1, 1) | 2093 SOR_XBAR_CTRL_LINK1_XSEL(0, 0) | 2094 SOR_XBAR_CTRL_LINK0_XSEL(4, 4) | 2095 SOR_XBAR_CTRL_LINK0_XSEL(3, 3) | 2096 SOR_XBAR_CTRL_LINK0_XSEL(2, 0) | 2097 SOR_XBAR_CTRL_LINK0_XSEL(1, 1) | 2098 SOR_XBAR_CTRL_LINK0_XSEL(0, 2); 2099 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2100 2101 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2102 2103 /* switch to parent clock */ 2104 err = tegra_sor_set_parent_clock(sor, sor->clk_parent); 2105 if (err < 0) 2106 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 2107 2108 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2109 2110 /* XXX is this the proper check? */ 2111 if (mode->clock < 75000) 2112 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; 2113 2114 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); 2115 2116 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; 2117 2118 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | 2119 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); 2120 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); 2121 2122 /* H_PULSE2 setup */ 2123 pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) + 2124 (mode->htotal - mode->hsync_end) - 10; 2125 2126 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | 2127 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; 2128 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 2129 2130 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); 2131 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 2132 2133 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); 2134 value |= H_PULSE2_ENABLE; 2135 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); 2136 2137 /* infoframe setup */ 2138 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); 2139 if (err < 0) 2140 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2141 2142 /* XXX HDMI audio support not implemented yet */ 2143 tegra_sor_hdmi_disable_audio_infoframe(sor); 2144 2145 /* use single TMDS protocol */ 2146 value = tegra_sor_readl(sor, SOR_STATE1); 2147 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2148 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; 2149 tegra_sor_writel(sor, value, SOR_STATE1); 2150 2151 /* power up pad calibration */ 2152 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2153 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 2154 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2155 2156 /* production settings */ 2157 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); 2158 if (!settings) { 2159 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", 2160 mode->clock * 1000); 2161 return; 2162 } 2163 2164 value = tegra_sor_readl(sor, SOR_PLL0); 2165 value &= ~SOR_PLL0_ICHPMP_MASK; 2166 value &= ~SOR_PLL0_VCOCAP_MASK; 2167 value |= SOR_PLL0_ICHPMP(settings->ichpmp); 2168 value |= SOR_PLL0_VCOCAP(settings->vcocap); 2169 tegra_sor_writel(sor, value, SOR_PLL0); 2170 2171 tegra_sor_dp_term_calibrate(sor); 2172 2173 value = tegra_sor_readl(sor, SOR_PLL1); 2174 value &= ~SOR_PLL1_LOADADJ_MASK; 2175 value |= SOR_PLL1_LOADADJ(settings->loadadj); 2176 tegra_sor_writel(sor, value, SOR_PLL1); 2177 2178 value = tegra_sor_readl(sor, SOR_PLL3); 2179 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; 2180 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref); 2181 tegra_sor_writel(sor, value, SOR_PLL3); 2182 2183 value = settings->drive_current[0] << 24 | 2184 settings->drive_current[1] << 16 | 2185 settings->drive_current[2] << 8 | 2186 settings->drive_current[3] << 0; 2187 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 2188 2189 value = settings->preemphasis[0] << 24 | 2190 settings->preemphasis[1] << 16 | 2191 settings->preemphasis[2] << 8 | 2192 settings->preemphasis[3] << 0; 2193 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 2194 2195 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2196 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 2197 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 2198 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu); 2199 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2200 2201 /* power down pad calibration */ 2202 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2203 value |= SOR_DP_PADCTL_PAD_CAL_PD; 2204 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2205 2206 /* miscellaneous display controller settings */ 2207 value = VSYNC_H_POSITION(1); 2208 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); 2209 2210 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2211 value &= ~DITHER_CONTROL_MASK; 2212 value &= ~BASE_COLOR_SIZE_MASK; 2213 2214 switch (state->bpc) { 2215 case 6: 2216 value |= BASE_COLOR_SIZE_666; 2217 break; 2218 2219 case 8: 2220 value |= BASE_COLOR_SIZE_888; 2221 break; 2222 2223 default: 2224 WARN(1, "%u bits-per-color not supported\n", state->bpc); 2225 value |= BASE_COLOR_SIZE_888; 2226 break; 2227 } 2228 2229 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2230 2231 err = tegra_sor_power_up(sor, 250); 2232 if (err < 0) 2233 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2234 2235 /* configure dynamic range of output */ 2236 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); 2237 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; 2238 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; 2239 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); 2240 2241 /* configure colorspace */ 2242 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); 2243 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; 2244 value |= SOR_HEAD_STATE_COLORSPACE_RGB; 2245 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); 2246 2247 tegra_sor_mode_set(sor, mode, state); 2248 2249 tegra_sor_update(sor); 2250 2251 err = tegra_sor_attach(sor); 2252 if (err < 0) 2253 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2254 2255 /* enable display to SOR clock and generate HDMI preamble */ 2256 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2257 value |= SOR1_ENABLE | SOR1_TIMING_CYA; 2258 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2259 2260 tegra_dc_commit(dc); 2261 2262 err = tegra_sor_wakeup(sor); 2263 if (err < 0) 2264 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2265 } 2266 2267 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { 2268 .disable = tegra_sor_hdmi_disable, 2269 .enable = tegra_sor_hdmi_enable, 2270 .atomic_check = tegra_sor_encoder_atomic_check, 2271 }; 2272 2273 static int tegra_sor_init(struct host1x_client *client) 2274 { 2275 struct drm_device *drm = dev_get_drvdata(client->parent); 2276 const struct drm_encoder_helper_funcs *helpers = NULL; 2277 struct tegra_sor *sor = host1x_client_to_sor(client); 2278 int connector = DRM_MODE_CONNECTOR_Unknown; 2279 int encoder = DRM_MODE_ENCODER_NONE; 2280 int err; 2281 2282 if (!sor->aux) { 2283 if (sor->soc->supports_hdmi) { 2284 connector = DRM_MODE_CONNECTOR_HDMIA; 2285 encoder = DRM_MODE_ENCODER_TMDS; 2286 helpers = &tegra_sor_hdmi_helpers; 2287 } else if (sor->soc->supports_lvds) { 2288 connector = DRM_MODE_CONNECTOR_LVDS; 2289 encoder = DRM_MODE_ENCODER_LVDS; 2290 } 2291 } else { 2292 if (sor->soc->supports_edp) { 2293 connector = DRM_MODE_CONNECTOR_eDP; 2294 encoder = DRM_MODE_ENCODER_TMDS; 2295 helpers = &tegra_sor_edp_helpers; 2296 } else if (sor->soc->supports_dp) { 2297 connector = DRM_MODE_CONNECTOR_DisplayPort; 2298 encoder = DRM_MODE_ENCODER_TMDS; 2299 } 2300 } 2301 2302 sor->output.dev = sor->dev; 2303 2304 drm_connector_init(drm, &sor->output.connector, 2305 &tegra_sor_connector_funcs, 2306 connector); 2307 drm_connector_helper_add(&sor->output.connector, 2308 &tegra_sor_connector_helper_funcs); 2309 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; 2310 2311 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, 2312 encoder, NULL); 2313 drm_encoder_helper_add(&sor->output.encoder, helpers); 2314 2315 drm_mode_connector_attach_encoder(&sor->output.connector, 2316 &sor->output.encoder); 2317 drm_connector_register(&sor->output.connector); 2318 2319 err = tegra_output_init(drm, &sor->output); 2320 if (err < 0) { 2321 dev_err(client->dev, "failed to initialize output: %d\n", err); 2322 return err; 2323 } 2324 2325 sor->output.encoder.possible_crtcs = 0x3; 2326 2327 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 2328 err = tegra_sor_debugfs_init(sor, drm->primary); 2329 if (err < 0) 2330 dev_err(sor->dev, "debugfs setup failed: %d\n", err); 2331 } 2332 2333 if (sor->aux) { 2334 err = drm_dp_aux_attach(sor->aux, &sor->output); 2335 if (err < 0) { 2336 dev_err(sor->dev, "failed to attach DP: %d\n", err); 2337 return err; 2338 } 2339 } 2340 2341 /* 2342 * XXX: Remove this reset once proper hand-over from firmware to 2343 * kernel is possible. 2344 */ 2345 err = reset_control_assert(sor->rst); 2346 if (err < 0) { 2347 dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); 2348 return err; 2349 } 2350 2351 err = clk_prepare_enable(sor->clk); 2352 if (err < 0) { 2353 dev_err(sor->dev, "failed to enable clock: %d\n", err); 2354 return err; 2355 } 2356 2357 usleep_range(1000, 3000); 2358 2359 err = reset_control_deassert(sor->rst); 2360 if (err < 0) { 2361 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); 2362 return err; 2363 } 2364 2365 err = clk_prepare_enable(sor->clk_safe); 2366 if (err < 0) 2367 return err; 2368 2369 err = clk_prepare_enable(sor->clk_dp); 2370 if (err < 0) 2371 return err; 2372 2373 return 0; 2374 } 2375 2376 static int tegra_sor_exit(struct host1x_client *client) 2377 { 2378 struct tegra_sor *sor = host1x_client_to_sor(client); 2379 int err; 2380 2381 tegra_output_exit(&sor->output); 2382 2383 if (sor->aux) { 2384 err = drm_dp_aux_detach(sor->aux); 2385 if (err < 0) { 2386 dev_err(sor->dev, "failed to detach DP: %d\n", err); 2387 return err; 2388 } 2389 } 2390 2391 clk_disable_unprepare(sor->clk_safe); 2392 clk_disable_unprepare(sor->clk_dp); 2393 clk_disable_unprepare(sor->clk); 2394 2395 if (IS_ENABLED(CONFIG_DEBUG_FS)) 2396 tegra_sor_debugfs_exit(sor); 2397 2398 return 0; 2399 } 2400 2401 static const struct host1x_client_ops sor_client_ops = { 2402 .init = tegra_sor_init, 2403 .exit = tegra_sor_exit, 2404 }; 2405 2406 static const struct tegra_sor_ops tegra_sor_edp_ops = { 2407 .name = "eDP", 2408 }; 2409 2410 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) 2411 { 2412 int err; 2413 2414 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); 2415 if (IS_ERR(sor->avdd_io_supply)) { 2416 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", 2417 PTR_ERR(sor->avdd_io_supply)); 2418 return PTR_ERR(sor->avdd_io_supply); 2419 } 2420 2421 err = regulator_enable(sor->avdd_io_supply); 2422 if (err < 0) { 2423 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", 2424 err); 2425 return err; 2426 } 2427 2428 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); 2429 if (IS_ERR(sor->vdd_pll_supply)) { 2430 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", 2431 PTR_ERR(sor->vdd_pll_supply)); 2432 return PTR_ERR(sor->vdd_pll_supply); 2433 } 2434 2435 err = regulator_enable(sor->vdd_pll_supply); 2436 if (err < 0) { 2437 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", 2438 err); 2439 return err; 2440 } 2441 2442 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); 2443 if (IS_ERR(sor->hdmi_supply)) { 2444 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", 2445 PTR_ERR(sor->hdmi_supply)); 2446 return PTR_ERR(sor->hdmi_supply); 2447 } 2448 2449 err = regulator_enable(sor->hdmi_supply); 2450 if (err < 0) { 2451 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); 2452 return err; 2453 } 2454 2455 return 0; 2456 } 2457 2458 static int tegra_sor_hdmi_remove(struct tegra_sor *sor) 2459 { 2460 regulator_disable(sor->hdmi_supply); 2461 regulator_disable(sor->vdd_pll_supply); 2462 regulator_disable(sor->avdd_io_supply); 2463 2464 return 0; 2465 } 2466 2467 static const struct tegra_sor_ops tegra_sor_hdmi_ops = { 2468 .name = "HDMI", 2469 .probe = tegra_sor_hdmi_probe, 2470 .remove = tegra_sor_hdmi_remove, 2471 }; 2472 2473 static const struct tegra_sor_soc tegra124_sor = { 2474 .supports_edp = true, 2475 .supports_lvds = true, 2476 .supports_hdmi = false, 2477 .supports_dp = false, 2478 }; 2479 2480 static const struct tegra_sor_soc tegra210_sor = { 2481 .supports_edp = true, 2482 .supports_lvds = false, 2483 .supports_hdmi = false, 2484 .supports_dp = false, 2485 }; 2486 2487 static const struct tegra_sor_soc tegra210_sor1 = { 2488 .supports_edp = false, 2489 .supports_lvds = false, 2490 .supports_hdmi = true, 2491 .supports_dp = true, 2492 2493 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), 2494 .settings = tegra210_sor_hdmi_defaults, 2495 }; 2496 2497 static const struct of_device_id tegra_sor_of_match[] = { 2498 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, 2499 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, 2500 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, 2501 { }, 2502 }; 2503 MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 2504 2505 static int tegra_sor_probe(struct platform_device *pdev) 2506 { 2507 const struct of_device_id *match; 2508 struct device_node *np; 2509 struct tegra_sor *sor; 2510 struct resource *regs; 2511 int err; 2512 2513 match = of_match_device(tegra_sor_of_match, &pdev->dev); 2514 2515 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 2516 if (!sor) 2517 return -ENOMEM; 2518 2519 sor->output.dev = sor->dev = &pdev->dev; 2520 sor->soc = match->data; 2521 2522 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, 2523 sor->soc->num_settings * 2524 sizeof(*sor->settings), 2525 GFP_KERNEL); 2526 if (!sor->settings) 2527 return -ENOMEM; 2528 2529 sor->num_settings = sor->soc->num_settings; 2530 2531 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 2532 if (np) { 2533 sor->aux = drm_dp_aux_find_by_of_node(np); 2534 of_node_put(np); 2535 2536 if (!sor->aux) 2537 return -EPROBE_DEFER; 2538 } 2539 2540 if (!sor->aux) { 2541 if (sor->soc->supports_hdmi) { 2542 sor->ops = &tegra_sor_hdmi_ops; 2543 } else if (sor->soc->supports_lvds) { 2544 dev_err(&pdev->dev, "LVDS not supported yet\n"); 2545 return -ENODEV; 2546 } else { 2547 dev_err(&pdev->dev, "unknown (non-DP) support\n"); 2548 return -ENODEV; 2549 } 2550 } else { 2551 if (sor->soc->supports_edp) { 2552 sor->ops = &tegra_sor_edp_ops; 2553 } else if (sor->soc->supports_dp) { 2554 dev_err(&pdev->dev, "DisplayPort not supported yet\n"); 2555 return -ENODEV; 2556 } else { 2557 dev_err(&pdev->dev, "unknown (DP) support\n"); 2558 return -ENODEV; 2559 } 2560 } 2561 2562 err = tegra_output_probe(&sor->output); 2563 if (err < 0) { 2564 dev_err(&pdev->dev, "failed to probe output: %d\n", err); 2565 return err; 2566 } 2567 2568 if (sor->ops && sor->ops->probe) { 2569 err = sor->ops->probe(sor); 2570 if (err < 0) { 2571 dev_err(&pdev->dev, "failed to probe %s: %d\n", 2572 sor->ops->name, err); 2573 goto output; 2574 } 2575 } 2576 2577 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2578 sor->regs = devm_ioremap_resource(&pdev->dev, regs); 2579 if (IS_ERR(sor->regs)) { 2580 err = PTR_ERR(sor->regs); 2581 goto remove; 2582 } 2583 2584 sor->rst = devm_reset_control_get(&pdev->dev, "sor"); 2585 if (IS_ERR(sor->rst)) { 2586 err = PTR_ERR(sor->rst); 2587 dev_err(&pdev->dev, "failed to get reset control: %d\n", err); 2588 goto remove; 2589 } 2590 2591 sor->clk = devm_clk_get(&pdev->dev, NULL); 2592 if (IS_ERR(sor->clk)) { 2593 err = PTR_ERR(sor->clk); 2594 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); 2595 goto remove; 2596 } 2597 2598 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 2599 if (IS_ERR(sor->clk_parent)) { 2600 err = PTR_ERR(sor->clk_parent); 2601 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); 2602 goto remove; 2603 } 2604 2605 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 2606 if (IS_ERR(sor->clk_safe)) { 2607 err = PTR_ERR(sor->clk_safe); 2608 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); 2609 goto remove; 2610 } 2611 2612 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 2613 if (IS_ERR(sor->clk_dp)) { 2614 err = PTR_ERR(sor->clk_dp); 2615 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); 2616 goto remove; 2617 } 2618 2619 platform_set_drvdata(pdev, sor); 2620 pm_runtime_enable(&pdev->dev); 2621 2622 pm_runtime_get_sync(&pdev->dev); 2623 sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick"); 2624 pm_runtime_put(&pdev->dev); 2625 2626 if (IS_ERR(sor->clk_brick)) { 2627 err = PTR_ERR(sor->clk_brick); 2628 dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err); 2629 goto remove; 2630 } 2631 2632 INIT_LIST_HEAD(&sor->client.list); 2633 sor->client.ops = &sor_client_ops; 2634 sor->client.dev = &pdev->dev; 2635 2636 err = host1x_client_register(&sor->client); 2637 if (err < 0) { 2638 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 2639 err); 2640 goto remove; 2641 } 2642 2643 return 0; 2644 2645 remove: 2646 if (sor->ops && sor->ops->remove) 2647 sor->ops->remove(sor); 2648 output: 2649 tegra_output_remove(&sor->output); 2650 return err; 2651 } 2652 2653 static int tegra_sor_remove(struct platform_device *pdev) 2654 { 2655 struct tegra_sor *sor = platform_get_drvdata(pdev); 2656 int err; 2657 2658 pm_runtime_disable(&pdev->dev); 2659 2660 err = host1x_client_unregister(&sor->client); 2661 if (err < 0) { 2662 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 2663 err); 2664 return err; 2665 } 2666 2667 if (sor->ops && sor->ops->remove) { 2668 err = sor->ops->remove(sor); 2669 if (err < 0) 2670 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err); 2671 } 2672 2673 tegra_output_remove(&sor->output); 2674 2675 return 0; 2676 } 2677 2678 #ifdef CONFIG_PM 2679 static int tegra_sor_suspend(struct device *dev) 2680 { 2681 struct tegra_sor *sor = dev_get_drvdata(dev); 2682 int err; 2683 2684 err = reset_control_assert(sor->rst); 2685 if (err < 0) { 2686 dev_err(dev, "failed to assert reset: %d\n", err); 2687 return err; 2688 } 2689 2690 usleep_range(1000, 2000); 2691 2692 clk_disable_unprepare(sor->clk); 2693 2694 return 0; 2695 } 2696 2697 static int tegra_sor_resume(struct device *dev) 2698 { 2699 struct tegra_sor *sor = dev_get_drvdata(dev); 2700 int err; 2701 2702 err = clk_prepare_enable(sor->clk); 2703 if (err < 0) { 2704 dev_err(dev, "failed to enable clock: %d\n", err); 2705 return err; 2706 } 2707 2708 usleep_range(1000, 2000); 2709 2710 err = reset_control_deassert(sor->rst); 2711 if (err < 0) { 2712 dev_err(dev, "failed to deassert reset: %d\n", err); 2713 clk_disable_unprepare(sor->clk); 2714 return err; 2715 } 2716 2717 return 0; 2718 } 2719 #endif 2720 2721 static const struct dev_pm_ops tegra_sor_pm_ops = { 2722 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL) 2723 }; 2724 2725 struct platform_driver tegra_sor_driver = { 2726 .driver = { 2727 .name = "tegra-sor", 2728 .of_match_table = tegra_sor_of_match, 2729 .pm = &tegra_sor_pm_ops, 2730 }, 2731 .probe = tegra_sor_probe, 2732 .remove = tegra_sor_remove, 2733 }; 2734