1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/debugfs.h> 12 #include <linux/gpio.h> 13 #include <linux/io.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/reset.h> 19 20 #include <soc/tegra/pmc.h> 21 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_dp_helper.h> 24 #include <drm/drm_panel.h> 25 26 #include "dc.h" 27 #include "drm.h" 28 #include "sor.h" 29 30 #define SOR_REKEY 0x38 31 32 struct tegra_sor_hdmi_settings { 33 unsigned long frequency; 34 35 u8 vcocap; 36 u8 ichpmp; 37 u8 loadadj; 38 u8 termadj; 39 u8 tx_pu; 40 u8 bg_vref; 41 42 u8 drive_current[4]; 43 u8 preemphasis[4]; 44 }; 45 46 #if 1 47 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 48 { 49 .frequency = 54000000, 50 .vcocap = 0x0, 51 .ichpmp = 0x1, 52 .loadadj = 0x3, 53 .termadj = 0x9, 54 .tx_pu = 0x10, 55 .bg_vref = 0x8, 56 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 57 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 58 }, { 59 .frequency = 75000000, 60 .vcocap = 0x3, 61 .ichpmp = 0x1, 62 .loadadj = 0x3, 63 .termadj = 0x9, 64 .tx_pu = 0x40, 65 .bg_vref = 0x8, 66 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 67 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 68 }, { 69 .frequency = 150000000, 70 .vcocap = 0x3, 71 .ichpmp = 0x1, 72 .loadadj = 0x3, 73 .termadj = 0x9, 74 .tx_pu = 0x66, 75 .bg_vref = 0x8, 76 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 77 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 78 }, { 79 .frequency = 300000000, 80 .vcocap = 0x3, 81 .ichpmp = 0x1, 82 .loadadj = 0x3, 83 .termadj = 0x9, 84 .tx_pu = 0x66, 85 .bg_vref = 0xa, 86 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 87 .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, 88 }, { 89 .frequency = 600000000, 90 .vcocap = 0x3, 91 .ichpmp = 0x1, 92 .loadadj = 0x3, 93 .termadj = 0x9, 94 .tx_pu = 0x66, 95 .bg_vref = 0x8, 96 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 97 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 98 }, 99 }; 100 #else 101 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 102 { 103 .frequency = 75000000, 104 .vcocap = 0x3, 105 .ichpmp = 0x1, 106 .loadadj = 0x3, 107 .termadj = 0x9, 108 .tx_pu = 0x40, 109 .bg_vref = 0x8, 110 .drive_current = { 0x29, 0x29, 0x29, 0x29 }, 111 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 112 }, { 113 .frequency = 150000000, 114 .vcocap = 0x3, 115 .ichpmp = 0x1, 116 .loadadj = 0x3, 117 .termadj = 0x9, 118 .tx_pu = 0x66, 119 .bg_vref = 0x8, 120 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 121 .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, 122 }, { 123 .frequency = 300000000, 124 .vcocap = 0x3, 125 .ichpmp = 0x6, 126 .loadadj = 0x3, 127 .termadj = 0x9, 128 .tx_pu = 0x66, 129 .bg_vref = 0xf, 130 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 131 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, 132 }, { 133 .frequency = 600000000, 134 .vcocap = 0x3, 135 .ichpmp = 0xa, 136 .loadadj = 0x3, 137 .termadj = 0xb, 138 .tx_pu = 0x66, 139 .bg_vref = 0xe, 140 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, 141 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, 142 }, 143 }; 144 #endif 145 146 struct tegra_sor_soc { 147 bool supports_edp; 148 bool supports_lvds; 149 bool supports_hdmi; 150 bool supports_dp; 151 152 const struct tegra_sor_hdmi_settings *settings; 153 unsigned int num_settings; 154 }; 155 156 struct tegra_sor; 157 158 struct tegra_sor_ops { 159 const char *name; 160 int (*probe)(struct tegra_sor *sor); 161 int (*remove)(struct tegra_sor *sor); 162 }; 163 164 struct tegra_sor { 165 struct host1x_client client; 166 struct tegra_output output; 167 struct device *dev; 168 169 const struct tegra_sor_soc *soc; 170 void __iomem *regs; 171 172 struct reset_control *rst; 173 struct clk *clk_parent; 174 struct clk *clk_brick; 175 struct clk *clk_safe; 176 struct clk *clk_src; 177 struct clk *clk_dp; 178 struct clk *clk; 179 180 struct drm_dp_aux *aux; 181 182 struct drm_info_list *debugfs_files; 183 struct drm_minor *minor; 184 struct dentry *debugfs; 185 186 const struct tegra_sor_ops *ops; 187 188 /* for HDMI 2.0 */ 189 struct tegra_sor_hdmi_settings *settings; 190 unsigned int num_settings; 191 192 struct regulator *avdd_io_supply; 193 struct regulator *vdd_pll_supply; 194 struct regulator *hdmi_supply; 195 }; 196 197 struct tegra_sor_state { 198 struct drm_connector_state base; 199 200 unsigned int bpc; 201 }; 202 203 static inline struct tegra_sor_state * 204 to_sor_state(struct drm_connector_state *state) 205 { 206 return container_of(state, struct tegra_sor_state, base); 207 } 208 209 struct tegra_sor_config { 210 u32 bits_per_pixel; 211 212 u32 active_polarity; 213 u32 active_count; 214 u32 tu_size; 215 u32 active_frac; 216 u32 watermark; 217 218 u32 hblank_symbols; 219 u32 vblank_symbols; 220 }; 221 222 static inline struct tegra_sor * 223 host1x_client_to_sor(struct host1x_client *client) 224 { 225 return container_of(client, struct tegra_sor, client); 226 } 227 228 static inline struct tegra_sor *to_sor(struct tegra_output *output) 229 { 230 return container_of(output, struct tegra_sor, output); 231 } 232 233 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) 234 { 235 return readl(sor->regs + (offset << 2)); 236 } 237 238 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, 239 unsigned long offset) 240 { 241 writel(value, sor->regs + (offset << 2)); 242 } 243 244 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) 245 { 246 int err; 247 248 clk_disable_unprepare(sor->clk); 249 250 err = clk_set_parent(sor->clk, parent); 251 if (err < 0) 252 return err; 253 254 err = clk_prepare_enable(sor->clk); 255 if (err < 0) 256 return err; 257 258 return 0; 259 } 260 261 struct tegra_clk_sor_brick { 262 struct clk_hw hw; 263 struct tegra_sor *sor; 264 }; 265 266 static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw) 267 { 268 return container_of(hw, struct tegra_clk_sor_brick, hw); 269 } 270 271 static const char * const tegra_clk_sor_brick_parents[] = { 272 "pll_d2_out0", "pll_dp" 273 }; 274 275 static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index) 276 { 277 struct tegra_clk_sor_brick *brick = to_brick(hw); 278 struct tegra_sor *sor = brick->sor; 279 u32 value; 280 281 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 282 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 283 284 switch (index) { 285 case 0: 286 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 287 break; 288 289 case 1: 290 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 291 break; 292 } 293 294 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 295 296 return 0; 297 } 298 299 static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw) 300 { 301 struct tegra_clk_sor_brick *brick = to_brick(hw); 302 struct tegra_sor *sor = brick->sor; 303 u8 parent = U8_MAX; 304 u32 value; 305 306 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 307 308 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { 309 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: 310 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK: 311 parent = 0; 312 break; 313 314 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK: 315 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK: 316 parent = 1; 317 break; 318 } 319 320 return parent; 321 } 322 323 static const struct clk_ops tegra_clk_sor_brick_ops = { 324 .set_parent = tegra_clk_sor_brick_set_parent, 325 .get_parent = tegra_clk_sor_brick_get_parent, 326 }; 327 328 static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor, 329 const char *name) 330 { 331 struct tegra_clk_sor_brick *brick; 332 struct clk_init_data init; 333 struct clk *clk; 334 335 brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL); 336 if (!brick) 337 return ERR_PTR(-ENOMEM); 338 339 brick->sor = sor; 340 341 init.name = name; 342 init.flags = 0; 343 init.parent_names = tegra_clk_sor_brick_parents; 344 init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents); 345 init.ops = &tegra_clk_sor_brick_ops; 346 347 brick->hw.init = &init; 348 349 clk = devm_clk_register(sor->dev, &brick->hw); 350 if (IS_ERR(clk)) 351 kfree(brick); 352 353 return clk; 354 } 355 356 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, 357 struct drm_dp_link *link) 358 { 359 unsigned int i; 360 u8 pattern; 361 u32 value; 362 int err; 363 364 /* setup lane parameters */ 365 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | 366 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | 367 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | 368 SOR_LANE_DRIVE_CURRENT_LANE0(0x40); 369 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 370 371 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | 372 SOR_LANE_PREEMPHASIS_LANE2(0x0f) | 373 SOR_LANE_PREEMPHASIS_LANE1(0x0f) | 374 SOR_LANE_PREEMPHASIS_LANE0(0x0f); 375 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 376 377 value = SOR_LANE_POSTCURSOR_LANE3(0x00) | 378 SOR_LANE_POSTCURSOR_LANE2(0x00) | 379 SOR_LANE_POSTCURSOR_LANE1(0x00) | 380 SOR_LANE_POSTCURSOR_LANE0(0x00); 381 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); 382 383 /* disable LVDS mode */ 384 tegra_sor_writel(sor, 0, SOR_LVDS); 385 386 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 387 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 388 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 389 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ 390 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 391 392 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 393 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 394 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; 395 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 396 397 usleep_range(10, 100); 398 399 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 400 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 401 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 402 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 403 404 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); 405 if (err < 0) 406 return err; 407 408 for (i = 0, value = 0; i < link->num_lanes; i++) { 409 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 410 SOR_DP_TPG_SCRAMBLER_NONE | 411 SOR_DP_TPG_PATTERN_TRAIN1; 412 value = (value << 8) | lane; 413 } 414 415 tegra_sor_writel(sor, value, SOR_DP_TPG); 416 417 pattern = DP_TRAINING_PATTERN_1; 418 419 err = drm_dp_aux_train(sor->aux, link, pattern); 420 if (err < 0) 421 return err; 422 423 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 424 value |= SOR_DP_SPARE_SEQ_ENABLE; 425 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 426 value |= SOR_DP_SPARE_MACRO_SOR_CLK; 427 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 428 429 for (i = 0, value = 0; i < link->num_lanes; i++) { 430 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 431 SOR_DP_TPG_SCRAMBLER_NONE | 432 SOR_DP_TPG_PATTERN_TRAIN2; 433 value = (value << 8) | lane; 434 } 435 436 tegra_sor_writel(sor, value, SOR_DP_TPG); 437 438 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; 439 440 err = drm_dp_aux_train(sor->aux, link, pattern); 441 if (err < 0) 442 return err; 443 444 for (i = 0, value = 0; i < link->num_lanes; i++) { 445 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 446 SOR_DP_TPG_SCRAMBLER_GALIOS | 447 SOR_DP_TPG_PATTERN_NONE; 448 value = (value << 8) | lane; 449 } 450 451 tegra_sor_writel(sor, value, SOR_DP_TPG); 452 453 pattern = DP_TRAINING_PATTERN_DISABLE; 454 455 err = drm_dp_aux_train(sor->aux, link, pattern); 456 if (err < 0) 457 return err; 458 459 return 0; 460 } 461 462 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) 463 { 464 u32 mask = 0x08, adj = 0, value; 465 466 /* enable pad calibration logic */ 467 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 468 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 469 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 470 471 value = tegra_sor_readl(sor, SOR_PLL1); 472 value |= SOR_PLL1_TMDS_TERM; 473 tegra_sor_writel(sor, value, SOR_PLL1); 474 475 while (mask) { 476 adj |= mask; 477 478 value = tegra_sor_readl(sor, SOR_PLL1); 479 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 480 value |= SOR_PLL1_TMDS_TERMADJ(adj); 481 tegra_sor_writel(sor, value, SOR_PLL1); 482 483 usleep_range(100, 200); 484 485 value = tegra_sor_readl(sor, SOR_PLL1); 486 if (value & SOR_PLL1_TERM_COMPOUT) 487 adj &= ~mask; 488 489 mask >>= 1; 490 } 491 492 value = tegra_sor_readl(sor, SOR_PLL1); 493 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 494 value |= SOR_PLL1_TMDS_TERMADJ(adj); 495 tegra_sor_writel(sor, value, SOR_PLL1); 496 497 /* disable pad calibration logic */ 498 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 499 value |= SOR_DP_PADCTL_PAD_CAL_PD; 500 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 501 } 502 503 static void tegra_sor_super_update(struct tegra_sor *sor) 504 { 505 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 506 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); 507 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 508 } 509 510 static void tegra_sor_update(struct tegra_sor *sor) 511 { 512 tegra_sor_writel(sor, 0, SOR_STATE0); 513 tegra_sor_writel(sor, 1, SOR_STATE0); 514 tegra_sor_writel(sor, 0, SOR_STATE0); 515 } 516 517 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 518 { 519 u32 value; 520 521 value = tegra_sor_readl(sor, SOR_PWM_DIV); 522 value &= ~SOR_PWM_DIV_MASK; 523 value |= 0x400; /* period */ 524 tegra_sor_writel(sor, value, SOR_PWM_DIV); 525 526 value = tegra_sor_readl(sor, SOR_PWM_CTL); 527 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 528 value |= 0x400; /* duty cycle */ 529 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 530 value |= SOR_PWM_CTL_TRIGGER; 531 tegra_sor_writel(sor, value, SOR_PWM_CTL); 532 533 timeout = jiffies + msecs_to_jiffies(timeout); 534 535 while (time_before(jiffies, timeout)) { 536 value = tegra_sor_readl(sor, SOR_PWM_CTL); 537 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 538 return 0; 539 540 usleep_range(25, 100); 541 } 542 543 return -ETIMEDOUT; 544 } 545 546 static int tegra_sor_attach(struct tegra_sor *sor) 547 { 548 unsigned long value, timeout; 549 550 /* wake up in normal mode */ 551 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 552 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 553 value |= SOR_SUPER_STATE_MODE_NORMAL; 554 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 555 tegra_sor_super_update(sor); 556 557 /* attach */ 558 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 559 value |= SOR_SUPER_STATE_ATTACHED; 560 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 561 tegra_sor_super_update(sor); 562 563 timeout = jiffies + msecs_to_jiffies(250); 564 565 while (time_before(jiffies, timeout)) { 566 value = tegra_sor_readl(sor, SOR_TEST); 567 if ((value & SOR_TEST_ATTACHED) != 0) 568 return 0; 569 570 usleep_range(25, 100); 571 } 572 573 return -ETIMEDOUT; 574 } 575 576 static int tegra_sor_wakeup(struct tegra_sor *sor) 577 { 578 unsigned long value, timeout; 579 580 timeout = jiffies + msecs_to_jiffies(250); 581 582 /* wait for head to wake up */ 583 while (time_before(jiffies, timeout)) { 584 value = tegra_sor_readl(sor, SOR_TEST); 585 value &= SOR_TEST_HEAD_MODE_MASK; 586 587 if (value == SOR_TEST_HEAD_MODE_AWAKE) 588 return 0; 589 590 usleep_range(25, 100); 591 } 592 593 return -ETIMEDOUT; 594 } 595 596 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 597 { 598 u32 value; 599 600 value = tegra_sor_readl(sor, SOR_PWR); 601 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 602 tegra_sor_writel(sor, value, SOR_PWR); 603 604 timeout = jiffies + msecs_to_jiffies(timeout); 605 606 while (time_before(jiffies, timeout)) { 607 value = tegra_sor_readl(sor, SOR_PWR); 608 if ((value & SOR_PWR_TRIGGER) == 0) 609 return 0; 610 611 usleep_range(25, 100); 612 } 613 614 return -ETIMEDOUT; 615 } 616 617 struct tegra_sor_params { 618 /* number of link clocks per line */ 619 unsigned int num_clocks; 620 /* ratio between input and output */ 621 u64 ratio; 622 /* precision factor */ 623 u64 precision; 624 625 unsigned int active_polarity; 626 unsigned int active_count; 627 unsigned int active_frac; 628 unsigned int tu_size; 629 unsigned int error; 630 }; 631 632 static int tegra_sor_compute_params(struct tegra_sor *sor, 633 struct tegra_sor_params *params, 634 unsigned int tu_size) 635 { 636 u64 active_sym, active_count, frac, approx; 637 u32 active_polarity, active_frac = 0; 638 const u64 f = params->precision; 639 s64 error; 640 641 active_sym = params->ratio * tu_size; 642 active_count = div_u64(active_sym, f) * f; 643 frac = active_sym - active_count; 644 645 /* fraction < 0.5 */ 646 if (frac >= (f / 2)) { 647 active_polarity = 1; 648 frac = f - frac; 649 } else { 650 active_polarity = 0; 651 } 652 653 if (frac != 0) { 654 frac = div_u64(f * f, frac); /* 1/fraction */ 655 if (frac <= (15 * f)) { 656 active_frac = div_u64(frac, f); 657 658 /* round up */ 659 if (active_polarity) 660 active_frac++; 661 } else { 662 active_frac = active_polarity ? 1 : 15; 663 } 664 } 665 666 if (active_frac == 1) 667 active_polarity = 0; 668 669 if (active_polarity == 1) { 670 if (active_frac) { 671 approx = active_count + (active_frac * (f - 1)) * f; 672 approx = div_u64(approx, active_frac * f); 673 } else { 674 approx = active_count + f; 675 } 676 } else { 677 if (active_frac) 678 approx = active_count + div_u64(f, active_frac); 679 else 680 approx = active_count; 681 } 682 683 error = div_s64(active_sym - approx, tu_size); 684 error *= params->num_clocks; 685 686 if (error <= 0 && abs(error) < params->error) { 687 params->active_count = div_u64(active_count, f); 688 params->active_polarity = active_polarity; 689 params->active_frac = active_frac; 690 params->error = abs(error); 691 params->tu_size = tu_size; 692 693 if (error == 0) 694 return true; 695 } 696 697 return false; 698 } 699 700 static int tegra_sor_compute_config(struct tegra_sor *sor, 701 const struct drm_display_mode *mode, 702 struct tegra_sor_config *config, 703 struct drm_dp_link *link) 704 { 705 const u64 f = 100000, link_rate = link->rate * 1000; 706 const u64 pclk = mode->clock * 1000; 707 u64 input, output, watermark, num; 708 struct tegra_sor_params params; 709 u32 num_syms_per_line; 710 unsigned int i; 711 712 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) 713 return -EINVAL; 714 715 output = link_rate * 8 * link->num_lanes; 716 input = pclk * config->bits_per_pixel; 717 718 if (input >= output) 719 return -ERANGE; 720 721 memset(¶ms, 0, sizeof(params)); 722 params.ratio = div64_u64(input * f, output); 723 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 724 params.precision = f; 725 params.error = 64 * f; 726 params.tu_size = 64; 727 728 for (i = params.tu_size; i >= 32; i--) 729 if (tegra_sor_compute_params(sor, ¶ms, i)) 730 break; 731 732 if (params.active_frac == 0) { 733 config->active_polarity = 0; 734 config->active_count = params.active_count; 735 736 if (!params.active_polarity) 737 config->active_count--; 738 739 config->tu_size = params.tu_size; 740 config->active_frac = 1; 741 } else { 742 config->active_polarity = params.active_polarity; 743 config->active_count = params.active_count; 744 config->active_frac = params.active_frac; 745 config->tu_size = params.tu_size; 746 } 747 748 dev_dbg(sor->dev, 749 "polarity: %d active count: %d tu size: %d active frac: %d\n", 750 config->active_polarity, config->active_count, 751 config->tu_size, config->active_frac); 752 753 watermark = params.ratio * config->tu_size * (f - params.ratio); 754 watermark = div_u64(watermark, f); 755 756 watermark = div_u64(watermark + params.error, f); 757 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 758 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 759 (link->num_lanes * 8); 760 761 if (config->watermark > 30) { 762 config->watermark = 30; 763 dev_err(sor->dev, 764 "unable to compute TU size, forcing watermark to %u\n", 765 config->watermark); 766 } else if (config->watermark > num_syms_per_line) { 767 config->watermark = num_syms_per_line; 768 dev_err(sor->dev, "watermark too high, forcing to %u\n", 769 config->watermark); 770 } 771 772 /* compute the number of symbols per horizontal blanking interval */ 773 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 774 config->hblank_symbols = div_u64(num, pclk); 775 776 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 777 config->hblank_symbols -= 3; 778 779 config->hblank_symbols -= 12 / link->num_lanes; 780 781 /* compute the number of symbols per vertical blanking interval */ 782 num = (mode->hdisplay - 25) * link_rate; 783 config->vblank_symbols = div_u64(num, pclk); 784 config->vblank_symbols -= 36 / link->num_lanes + 4; 785 786 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 787 config->vblank_symbols); 788 789 return 0; 790 } 791 792 static void tegra_sor_apply_config(struct tegra_sor *sor, 793 const struct tegra_sor_config *config) 794 { 795 u32 value; 796 797 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 798 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 799 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); 800 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 801 802 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); 803 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 804 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); 805 806 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 807 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); 808 809 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 810 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); 811 812 if (config->active_polarity) 813 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 814 else 815 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 816 817 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 818 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 819 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); 820 821 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 822 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 823 value |= config->hblank_symbols & 0xffff; 824 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 825 826 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 827 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 828 value |= config->vblank_symbols & 0xffff; 829 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 830 } 831 832 static void tegra_sor_mode_set(struct tegra_sor *sor, 833 const struct drm_display_mode *mode, 834 struct tegra_sor_state *state) 835 { 836 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 837 unsigned int vbe, vse, hbe, hse, vbs, hbs; 838 u32 value; 839 840 value = tegra_sor_readl(sor, SOR_STATE1); 841 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; 842 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 843 value &= ~SOR_STATE_ASY_OWNER_MASK; 844 845 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | 846 SOR_STATE_ASY_OWNER(dc->pipe + 1); 847 848 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 849 value &= ~SOR_STATE_ASY_HSYNCPOL; 850 851 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 852 value |= SOR_STATE_ASY_HSYNCPOL; 853 854 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 855 value &= ~SOR_STATE_ASY_VSYNCPOL; 856 857 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 858 value |= SOR_STATE_ASY_VSYNCPOL; 859 860 switch (state->bpc) { 861 case 16: 862 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; 863 break; 864 865 case 12: 866 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; 867 break; 868 869 case 10: 870 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; 871 break; 872 873 case 8: 874 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 875 break; 876 877 case 6: 878 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 879 break; 880 881 default: 882 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 883 break; 884 } 885 886 tegra_sor_writel(sor, value, SOR_STATE1); 887 888 /* 889 * TODO: The video timing programming below doesn't seem to match the 890 * register definitions. 891 */ 892 893 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 894 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe)); 895 896 /* sync end = sync width - 1 */ 897 vse = mode->vsync_end - mode->vsync_start - 1; 898 hse = mode->hsync_end - mode->hsync_start - 1; 899 900 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 901 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe)); 902 903 /* blank end = sync end + back porch */ 904 vbe = vse + (mode->vtotal - mode->vsync_end); 905 hbe = hse + (mode->htotal - mode->hsync_end); 906 907 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 908 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe)); 909 910 /* blank start = blank end + active */ 911 vbs = vbe + mode->vdisplay; 912 hbs = hbe + mode->hdisplay; 913 914 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 915 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe)); 916 917 /* XXX interlacing support */ 918 tegra_sor_writel(sor, 0x001, SOR_HEAD_STATE5(dc->pipe)); 919 } 920 921 static int tegra_sor_detach(struct tegra_sor *sor) 922 { 923 unsigned long value, timeout; 924 925 /* switch to safe mode */ 926 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 927 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 928 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 929 tegra_sor_super_update(sor); 930 931 timeout = jiffies + msecs_to_jiffies(250); 932 933 while (time_before(jiffies, timeout)) { 934 value = tegra_sor_readl(sor, SOR_PWR); 935 if (value & SOR_PWR_MODE_SAFE) 936 break; 937 } 938 939 if ((value & SOR_PWR_MODE_SAFE) == 0) 940 return -ETIMEDOUT; 941 942 /* go to sleep */ 943 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 944 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 945 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 946 tegra_sor_super_update(sor); 947 948 /* detach */ 949 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 950 value &= ~SOR_SUPER_STATE_ATTACHED; 951 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 952 tegra_sor_super_update(sor); 953 954 timeout = jiffies + msecs_to_jiffies(250); 955 956 while (time_before(jiffies, timeout)) { 957 value = tegra_sor_readl(sor, SOR_TEST); 958 if ((value & SOR_TEST_ATTACHED) == 0) 959 break; 960 961 usleep_range(25, 100); 962 } 963 964 if ((value & SOR_TEST_ATTACHED) != 0) 965 return -ETIMEDOUT; 966 967 return 0; 968 } 969 970 static int tegra_sor_power_down(struct tegra_sor *sor) 971 { 972 unsigned long value, timeout; 973 int err; 974 975 value = tegra_sor_readl(sor, SOR_PWR); 976 value &= ~SOR_PWR_NORMAL_STATE_PU; 977 value |= SOR_PWR_TRIGGER; 978 tegra_sor_writel(sor, value, SOR_PWR); 979 980 timeout = jiffies + msecs_to_jiffies(250); 981 982 while (time_before(jiffies, timeout)) { 983 value = tegra_sor_readl(sor, SOR_PWR); 984 if ((value & SOR_PWR_TRIGGER) == 0) 985 return 0; 986 987 usleep_range(25, 100); 988 } 989 990 if ((value & SOR_PWR_TRIGGER) != 0) 991 return -ETIMEDOUT; 992 993 /* switch to safe parent clock */ 994 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 995 if (err < 0) 996 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 997 998 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 999 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 1000 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 1001 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1002 1003 /* stop lane sequencer */ 1004 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 1005 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 1006 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 1007 1008 timeout = jiffies + msecs_to_jiffies(250); 1009 1010 while (time_before(jiffies, timeout)) { 1011 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 1012 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 1013 break; 1014 1015 usleep_range(25, 100); 1016 } 1017 1018 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 1019 return -ETIMEDOUT; 1020 1021 value = tegra_sor_readl(sor, SOR_PLL2); 1022 value |= SOR_PLL2_PORT_POWERDOWN; 1023 tegra_sor_writel(sor, value, SOR_PLL2); 1024 1025 usleep_range(20, 100); 1026 1027 value = tegra_sor_readl(sor, SOR_PLL0); 1028 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1029 tegra_sor_writel(sor, value, SOR_PLL0); 1030 1031 value = tegra_sor_readl(sor, SOR_PLL2); 1032 value |= SOR_PLL2_SEQ_PLLCAPPD; 1033 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1034 tegra_sor_writel(sor, value, SOR_PLL2); 1035 1036 usleep_range(20, 100); 1037 1038 return 0; 1039 } 1040 1041 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 1042 { 1043 u32 value; 1044 1045 timeout = jiffies + msecs_to_jiffies(timeout); 1046 1047 while (time_before(jiffies, timeout)) { 1048 value = tegra_sor_readl(sor, SOR_CRCA); 1049 if (value & SOR_CRCA_VALID) 1050 return 0; 1051 1052 usleep_range(100, 200); 1053 } 1054 1055 return -ETIMEDOUT; 1056 } 1057 1058 static int tegra_sor_show_crc(struct seq_file *s, void *data) 1059 { 1060 struct drm_info_node *node = s->private; 1061 struct tegra_sor *sor = node->info_ent->data; 1062 struct drm_crtc *crtc = sor->output.encoder.crtc; 1063 struct drm_device *drm = node->minor->dev; 1064 int err = 0; 1065 u32 value; 1066 1067 drm_modeset_lock_all(drm); 1068 1069 if (!crtc || !crtc->state->active) { 1070 err = -EBUSY; 1071 goto unlock; 1072 } 1073 1074 value = tegra_sor_readl(sor, SOR_STATE1); 1075 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1076 tegra_sor_writel(sor, value, SOR_STATE1); 1077 1078 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 1079 value |= SOR_CRC_CNTRL_ENABLE; 1080 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 1081 1082 value = tegra_sor_readl(sor, SOR_TEST); 1083 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 1084 tegra_sor_writel(sor, value, SOR_TEST); 1085 1086 err = tegra_sor_crc_wait(sor, 100); 1087 if (err < 0) 1088 goto unlock; 1089 1090 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); 1091 value = tegra_sor_readl(sor, SOR_CRCB); 1092 1093 seq_printf(s, "%08x\n", value); 1094 1095 unlock: 1096 drm_modeset_unlock_all(drm); 1097 return err; 1098 } 1099 1100 static int tegra_sor_show_regs(struct seq_file *s, void *data) 1101 { 1102 struct drm_info_node *node = s->private; 1103 struct tegra_sor *sor = node->info_ent->data; 1104 struct drm_crtc *crtc = sor->output.encoder.crtc; 1105 struct drm_device *drm = node->minor->dev; 1106 int err = 0; 1107 1108 drm_modeset_lock_all(drm); 1109 1110 if (!crtc || !crtc->state->active) { 1111 err = -EBUSY; 1112 goto unlock; 1113 } 1114 1115 #define DUMP_REG(name) \ 1116 seq_printf(s, "%-38s %#05x %08x\n", #name, name, \ 1117 tegra_sor_readl(sor, name)) 1118 1119 DUMP_REG(SOR_CTXSW); 1120 DUMP_REG(SOR_SUPER_STATE0); 1121 DUMP_REG(SOR_SUPER_STATE1); 1122 DUMP_REG(SOR_STATE0); 1123 DUMP_REG(SOR_STATE1); 1124 DUMP_REG(SOR_HEAD_STATE0(0)); 1125 DUMP_REG(SOR_HEAD_STATE0(1)); 1126 DUMP_REG(SOR_HEAD_STATE1(0)); 1127 DUMP_REG(SOR_HEAD_STATE1(1)); 1128 DUMP_REG(SOR_HEAD_STATE2(0)); 1129 DUMP_REG(SOR_HEAD_STATE2(1)); 1130 DUMP_REG(SOR_HEAD_STATE3(0)); 1131 DUMP_REG(SOR_HEAD_STATE3(1)); 1132 DUMP_REG(SOR_HEAD_STATE4(0)); 1133 DUMP_REG(SOR_HEAD_STATE4(1)); 1134 DUMP_REG(SOR_HEAD_STATE5(0)); 1135 DUMP_REG(SOR_HEAD_STATE5(1)); 1136 DUMP_REG(SOR_CRC_CNTRL); 1137 DUMP_REG(SOR_DP_DEBUG_MVID); 1138 DUMP_REG(SOR_CLK_CNTRL); 1139 DUMP_REG(SOR_CAP); 1140 DUMP_REG(SOR_PWR); 1141 DUMP_REG(SOR_TEST); 1142 DUMP_REG(SOR_PLL0); 1143 DUMP_REG(SOR_PLL1); 1144 DUMP_REG(SOR_PLL2); 1145 DUMP_REG(SOR_PLL3); 1146 DUMP_REG(SOR_CSTM); 1147 DUMP_REG(SOR_LVDS); 1148 DUMP_REG(SOR_CRCA); 1149 DUMP_REG(SOR_CRCB); 1150 DUMP_REG(SOR_BLANK); 1151 DUMP_REG(SOR_SEQ_CTL); 1152 DUMP_REG(SOR_LANE_SEQ_CTL); 1153 DUMP_REG(SOR_SEQ_INST(0)); 1154 DUMP_REG(SOR_SEQ_INST(1)); 1155 DUMP_REG(SOR_SEQ_INST(2)); 1156 DUMP_REG(SOR_SEQ_INST(3)); 1157 DUMP_REG(SOR_SEQ_INST(4)); 1158 DUMP_REG(SOR_SEQ_INST(5)); 1159 DUMP_REG(SOR_SEQ_INST(6)); 1160 DUMP_REG(SOR_SEQ_INST(7)); 1161 DUMP_REG(SOR_SEQ_INST(8)); 1162 DUMP_REG(SOR_SEQ_INST(9)); 1163 DUMP_REG(SOR_SEQ_INST(10)); 1164 DUMP_REG(SOR_SEQ_INST(11)); 1165 DUMP_REG(SOR_SEQ_INST(12)); 1166 DUMP_REG(SOR_SEQ_INST(13)); 1167 DUMP_REG(SOR_SEQ_INST(14)); 1168 DUMP_REG(SOR_SEQ_INST(15)); 1169 DUMP_REG(SOR_PWM_DIV); 1170 DUMP_REG(SOR_PWM_CTL); 1171 DUMP_REG(SOR_VCRC_A0); 1172 DUMP_REG(SOR_VCRC_A1); 1173 DUMP_REG(SOR_VCRC_B0); 1174 DUMP_REG(SOR_VCRC_B1); 1175 DUMP_REG(SOR_CCRC_A0); 1176 DUMP_REG(SOR_CCRC_A1); 1177 DUMP_REG(SOR_CCRC_B0); 1178 DUMP_REG(SOR_CCRC_B1); 1179 DUMP_REG(SOR_EDATA_A0); 1180 DUMP_REG(SOR_EDATA_A1); 1181 DUMP_REG(SOR_EDATA_B0); 1182 DUMP_REG(SOR_EDATA_B1); 1183 DUMP_REG(SOR_COUNT_A0); 1184 DUMP_REG(SOR_COUNT_A1); 1185 DUMP_REG(SOR_COUNT_B0); 1186 DUMP_REG(SOR_COUNT_B1); 1187 DUMP_REG(SOR_DEBUG_A0); 1188 DUMP_REG(SOR_DEBUG_A1); 1189 DUMP_REG(SOR_DEBUG_B0); 1190 DUMP_REG(SOR_DEBUG_B1); 1191 DUMP_REG(SOR_TRIG); 1192 DUMP_REG(SOR_MSCHECK); 1193 DUMP_REG(SOR_XBAR_CTRL); 1194 DUMP_REG(SOR_XBAR_POL); 1195 DUMP_REG(SOR_DP_LINKCTL0); 1196 DUMP_REG(SOR_DP_LINKCTL1); 1197 DUMP_REG(SOR_LANE_DRIVE_CURRENT0); 1198 DUMP_REG(SOR_LANE_DRIVE_CURRENT1); 1199 DUMP_REG(SOR_LANE4_DRIVE_CURRENT0); 1200 DUMP_REG(SOR_LANE4_DRIVE_CURRENT1); 1201 DUMP_REG(SOR_LANE_PREEMPHASIS0); 1202 DUMP_REG(SOR_LANE_PREEMPHASIS1); 1203 DUMP_REG(SOR_LANE4_PREEMPHASIS0); 1204 DUMP_REG(SOR_LANE4_PREEMPHASIS1); 1205 DUMP_REG(SOR_LANE_POSTCURSOR0); 1206 DUMP_REG(SOR_LANE_POSTCURSOR1); 1207 DUMP_REG(SOR_DP_CONFIG0); 1208 DUMP_REG(SOR_DP_CONFIG1); 1209 DUMP_REG(SOR_DP_MN0); 1210 DUMP_REG(SOR_DP_MN1); 1211 DUMP_REG(SOR_DP_PADCTL0); 1212 DUMP_REG(SOR_DP_PADCTL1); 1213 DUMP_REG(SOR_DP_DEBUG0); 1214 DUMP_REG(SOR_DP_DEBUG1); 1215 DUMP_REG(SOR_DP_SPARE0); 1216 DUMP_REG(SOR_DP_SPARE1); 1217 DUMP_REG(SOR_DP_AUDIO_CTRL); 1218 DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS); 1219 DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS); 1220 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER); 1221 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0); 1222 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1); 1223 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2); 1224 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3); 1225 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4); 1226 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5); 1227 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6); 1228 DUMP_REG(SOR_DP_TPG); 1229 DUMP_REG(SOR_DP_TPG_CONFIG); 1230 DUMP_REG(SOR_DP_LQ_CSTM0); 1231 DUMP_REG(SOR_DP_LQ_CSTM1); 1232 DUMP_REG(SOR_DP_LQ_CSTM2); 1233 1234 #undef DUMP_REG 1235 1236 unlock: 1237 drm_modeset_unlock_all(drm); 1238 return err; 1239 } 1240 1241 static const struct drm_info_list debugfs_files[] = { 1242 { "crc", tegra_sor_show_crc, 0, NULL }, 1243 { "regs", tegra_sor_show_regs, 0, NULL }, 1244 }; 1245 1246 static int tegra_sor_debugfs_init(struct tegra_sor *sor, 1247 struct drm_minor *minor) 1248 { 1249 const char *name = sor->soc->supports_dp ? "sor1" : "sor"; 1250 unsigned int i; 1251 int err; 1252 1253 sor->debugfs = debugfs_create_dir(name, minor->debugfs_root); 1254 if (!sor->debugfs) 1255 return -ENOMEM; 1256 1257 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1258 GFP_KERNEL); 1259 if (!sor->debugfs_files) { 1260 err = -ENOMEM; 1261 goto remove; 1262 } 1263 1264 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) 1265 sor->debugfs_files[i].data = sor; 1266 1267 err = drm_debugfs_create_files(sor->debugfs_files, 1268 ARRAY_SIZE(debugfs_files), 1269 sor->debugfs, minor); 1270 if (err < 0) 1271 goto free; 1272 1273 sor->minor = minor; 1274 1275 return 0; 1276 1277 free: 1278 kfree(sor->debugfs_files); 1279 sor->debugfs_files = NULL; 1280 remove: 1281 debugfs_remove_recursive(sor->debugfs); 1282 sor->debugfs = NULL; 1283 return err; 1284 } 1285 1286 static void tegra_sor_debugfs_exit(struct tegra_sor *sor) 1287 { 1288 drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files), 1289 sor->minor); 1290 sor->minor = NULL; 1291 1292 kfree(sor->debugfs_files); 1293 sor->debugfs_files = NULL; 1294 1295 debugfs_remove_recursive(sor->debugfs); 1296 sor->debugfs = NULL; 1297 } 1298 1299 static void tegra_sor_connector_reset(struct drm_connector *connector) 1300 { 1301 struct tegra_sor_state *state; 1302 1303 state = kzalloc(sizeof(*state), GFP_KERNEL); 1304 if (!state) 1305 return; 1306 1307 if (connector->state) { 1308 __drm_atomic_helper_connector_destroy_state(connector->state); 1309 kfree(connector->state); 1310 } 1311 1312 __drm_atomic_helper_connector_reset(connector, &state->base); 1313 } 1314 1315 static enum drm_connector_status 1316 tegra_sor_connector_detect(struct drm_connector *connector, bool force) 1317 { 1318 struct tegra_output *output = connector_to_output(connector); 1319 struct tegra_sor *sor = to_sor(output); 1320 1321 if (sor->aux) 1322 return drm_dp_aux_detect(sor->aux); 1323 1324 return tegra_output_connector_detect(connector, force); 1325 } 1326 1327 static struct drm_connector_state * 1328 tegra_sor_connector_duplicate_state(struct drm_connector *connector) 1329 { 1330 struct tegra_sor_state *state = to_sor_state(connector->state); 1331 struct tegra_sor_state *copy; 1332 1333 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 1334 if (!copy) 1335 return NULL; 1336 1337 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); 1338 1339 return ©->base; 1340 } 1341 1342 static const struct drm_connector_funcs tegra_sor_connector_funcs = { 1343 .dpms = drm_atomic_helper_connector_dpms, 1344 .reset = tegra_sor_connector_reset, 1345 .detect = tegra_sor_connector_detect, 1346 .fill_modes = drm_helper_probe_single_connector_modes, 1347 .destroy = tegra_output_connector_destroy, 1348 .atomic_duplicate_state = tegra_sor_connector_duplicate_state, 1349 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1350 }; 1351 1352 static int tegra_sor_connector_get_modes(struct drm_connector *connector) 1353 { 1354 struct tegra_output *output = connector_to_output(connector); 1355 struct tegra_sor *sor = to_sor(output); 1356 int err; 1357 1358 if (sor->aux) 1359 drm_dp_aux_enable(sor->aux); 1360 1361 err = tegra_output_connector_get_modes(connector); 1362 1363 if (sor->aux) 1364 drm_dp_aux_disable(sor->aux); 1365 1366 return err; 1367 } 1368 1369 static enum drm_mode_status 1370 tegra_sor_connector_mode_valid(struct drm_connector *connector, 1371 struct drm_display_mode *mode) 1372 { 1373 return MODE_OK; 1374 } 1375 1376 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { 1377 .get_modes = tegra_sor_connector_get_modes, 1378 .mode_valid = tegra_sor_connector_mode_valid, 1379 .best_encoder = tegra_output_connector_best_encoder, 1380 }; 1381 1382 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { 1383 .destroy = tegra_output_encoder_destroy, 1384 }; 1385 1386 static void tegra_sor_edp_disable(struct drm_encoder *encoder) 1387 { 1388 struct tegra_output *output = encoder_to_output(encoder); 1389 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1390 struct tegra_sor *sor = to_sor(output); 1391 u32 value; 1392 int err; 1393 1394 if (output->panel) 1395 drm_panel_disable(output->panel); 1396 1397 err = tegra_sor_detach(sor); 1398 if (err < 0) 1399 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1400 1401 tegra_sor_writel(sor, 0, SOR_STATE1); 1402 tegra_sor_update(sor); 1403 1404 /* 1405 * The following accesses registers of the display controller, so make 1406 * sure it's only executed when the output is attached to one. 1407 */ 1408 if (dc) { 1409 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1410 value &= ~SOR_ENABLE; 1411 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1412 1413 tegra_dc_commit(dc); 1414 } 1415 1416 err = tegra_sor_power_down(sor); 1417 if (err < 0) 1418 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1419 1420 if (sor->aux) { 1421 err = drm_dp_aux_disable(sor->aux); 1422 if (err < 0) 1423 dev_err(sor->dev, "failed to disable DP: %d\n", err); 1424 } 1425 1426 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); 1427 if (err < 0) 1428 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); 1429 1430 if (output->panel) 1431 drm_panel_unprepare(output->panel); 1432 1433 pm_runtime_put(sor->dev); 1434 } 1435 1436 #if 0 1437 static int calc_h_ref_to_sync(const struct drm_display_mode *mode, 1438 unsigned int *value) 1439 { 1440 unsigned int hfp, hsw, hbp, a = 0, b; 1441 1442 hfp = mode->hsync_start - mode->hdisplay; 1443 hsw = mode->hsync_end - mode->hsync_start; 1444 hbp = mode->htotal - mode->hsync_end; 1445 1446 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp); 1447 1448 b = hfp - 1; 1449 1450 pr_info("a: %u, b: %u\n", a, b); 1451 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp); 1452 1453 if (a + hsw + hbp <= 11) { 1454 a = 1 + 11 - hsw - hbp; 1455 pr_info("a: %u\n", a); 1456 } 1457 1458 if (a > b) 1459 return -EINVAL; 1460 1461 if (hsw < 1) 1462 return -EINVAL; 1463 1464 if (mode->hdisplay < 16) 1465 return -EINVAL; 1466 1467 if (value) { 1468 if (b > a && a % 2) 1469 *value = a + 1; 1470 else 1471 *value = a; 1472 } 1473 1474 return 0; 1475 } 1476 #endif 1477 1478 static void tegra_sor_edp_enable(struct drm_encoder *encoder) 1479 { 1480 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 1481 struct tegra_output *output = encoder_to_output(encoder); 1482 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1483 struct tegra_sor *sor = to_sor(output); 1484 struct tegra_sor_config config; 1485 struct tegra_sor_state *state; 1486 struct drm_dp_link link; 1487 u8 rate, lanes; 1488 unsigned int i; 1489 int err = 0; 1490 u32 value; 1491 1492 state = to_sor_state(output->connector.state); 1493 1494 pm_runtime_get_sync(sor->dev); 1495 1496 if (output->panel) 1497 drm_panel_prepare(output->panel); 1498 1499 err = drm_dp_aux_enable(sor->aux); 1500 if (err < 0) 1501 dev_err(sor->dev, "failed to enable DP: %d\n", err); 1502 1503 err = drm_dp_link_probe(sor->aux, &link); 1504 if (err < 0) { 1505 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 1506 return; 1507 } 1508 1509 /* switch to safe parent clock */ 1510 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1511 if (err < 0) 1512 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1513 1514 memset(&config, 0, sizeof(config)); 1515 config.bits_per_pixel = state->bpc * 3; 1516 1517 err = tegra_sor_compute_config(sor, mode, &config, &link); 1518 if (err < 0) 1519 dev_err(sor->dev, "failed to compute configuration: %d\n", err); 1520 1521 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1522 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 1523 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 1524 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1525 1526 value = tegra_sor_readl(sor, SOR_PLL2); 1527 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1528 tegra_sor_writel(sor, value, SOR_PLL2); 1529 usleep_range(20, 100); 1530 1531 value = tegra_sor_readl(sor, SOR_PLL3); 1532 value |= SOR_PLL3_PLL_VDD_MODE_3V3; 1533 tegra_sor_writel(sor, value, SOR_PLL3); 1534 1535 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | 1536 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; 1537 tegra_sor_writel(sor, value, SOR_PLL0); 1538 1539 value = tegra_sor_readl(sor, SOR_PLL2); 1540 value |= SOR_PLL2_SEQ_PLLCAPPD; 1541 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1542 value |= SOR_PLL2_LVDS_ENABLE; 1543 tegra_sor_writel(sor, value, SOR_PLL2); 1544 1545 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; 1546 tegra_sor_writel(sor, value, SOR_PLL1); 1547 1548 while (true) { 1549 value = tegra_sor_readl(sor, SOR_PLL2); 1550 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) 1551 break; 1552 1553 usleep_range(250, 1000); 1554 } 1555 1556 value = tegra_sor_readl(sor, SOR_PLL2); 1557 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 1558 value &= ~SOR_PLL2_PORT_POWERDOWN; 1559 tegra_sor_writel(sor, value, SOR_PLL2); 1560 1561 /* 1562 * power up 1563 */ 1564 1565 /* set safe link bandwidth (1.62 Gbps) */ 1566 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1567 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1568 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; 1569 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1570 1571 /* step 1 */ 1572 value = tegra_sor_readl(sor, SOR_PLL2); 1573 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | 1574 SOR_PLL2_BANDGAP_POWERDOWN; 1575 tegra_sor_writel(sor, value, SOR_PLL2); 1576 1577 value = tegra_sor_readl(sor, SOR_PLL0); 1578 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1579 tegra_sor_writel(sor, value, SOR_PLL0); 1580 1581 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1582 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 1583 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1584 1585 /* step 2 */ 1586 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); 1587 if (err < 0) 1588 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); 1589 1590 usleep_range(5, 100); 1591 1592 /* step 3 */ 1593 value = tegra_sor_readl(sor, SOR_PLL2); 1594 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1595 tegra_sor_writel(sor, value, SOR_PLL2); 1596 1597 usleep_range(20, 100); 1598 1599 /* step 4 */ 1600 value = tegra_sor_readl(sor, SOR_PLL0); 1601 value &= ~SOR_PLL0_VCOPD; 1602 value &= ~SOR_PLL0_PWR; 1603 tegra_sor_writel(sor, value, SOR_PLL0); 1604 1605 value = tegra_sor_readl(sor, SOR_PLL2); 1606 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1607 tegra_sor_writel(sor, value, SOR_PLL2); 1608 1609 usleep_range(200, 1000); 1610 1611 /* step 5 */ 1612 value = tegra_sor_readl(sor, SOR_PLL2); 1613 value &= ~SOR_PLL2_PORT_POWERDOWN; 1614 tegra_sor_writel(sor, value, SOR_PLL2); 1615 1616 /* switch to DP parent clock */ 1617 err = tegra_sor_set_parent_clock(sor, sor->clk_dp); 1618 if (err < 0) 1619 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 1620 1621 /* power DP lanes */ 1622 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1623 1624 if (link.num_lanes <= 2) 1625 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); 1626 else 1627 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; 1628 1629 if (link.num_lanes <= 1) 1630 value &= ~SOR_DP_PADCTL_PD_TXD_1; 1631 else 1632 value |= SOR_DP_PADCTL_PD_TXD_1; 1633 1634 if (link.num_lanes == 0) 1635 value &= ~SOR_DP_PADCTL_PD_TXD_0; 1636 else 1637 value |= SOR_DP_PADCTL_PD_TXD_0; 1638 1639 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1640 1641 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1642 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1643 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); 1644 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1645 1646 /* start lane sequencer */ 1647 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 1648 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 1649 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 1650 1651 while (true) { 1652 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 1653 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 1654 break; 1655 1656 usleep_range(250, 1000); 1657 } 1658 1659 /* set link bandwidth */ 1660 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1661 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1662 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; 1663 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1664 1665 tegra_sor_apply_config(sor, &config); 1666 1667 /* enable link */ 1668 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1669 value |= SOR_DP_LINKCTL_ENABLE; 1670 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 1671 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1672 1673 for (i = 0, value = 0; i < 4; i++) { 1674 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 1675 SOR_DP_TPG_SCRAMBLER_GALIOS | 1676 SOR_DP_TPG_PATTERN_NONE; 1677 value = (value << 8) | lane; 1678 } 1679 1680 tegra_sor_writel(sor, value, SOR_DP_TPG); 1681 1682 /* enable pad calibration logic */ 1683 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1684 value |= SOR_DP_PADCTL_PAD_CAL_PD; 1685 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 1686 1687 err = drm_dp_link_probe(sor->aux, &link); 1688 if (err < 0) 1689 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 1690 1691 err = drm_dp_link_power_up(sor->aux, &link); 1692 if (err < 0) 1693 dev_err(sor->dev, "failed to power up eDP link: %d\n", err); 1694 1695 err = drm_dp_link_configure(sor->aux, &link); 1696 if (err < 0) 1697 dev_err(sor->dev, "failed to configure eDP link: %d\n", err); 1698 1699 rate = drm_dp_link_rate_to_bw_code(link.rate); 1700 lanes = link.num_lanes; 1701 1702 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1703 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1704 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 1705 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1706 1707 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1708 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1709 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 1710 1711 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1712 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 1713 1714 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1715 1716 /* disable training pattern generator */ 1717 1718 for (i = 0; i < link.num_lanes; i++) { 1719 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 1720 SOR_DP_TPG_SCRAMBLER_GALIOS | 1721 SOR_DP_TPG_PATTERN_NONE; 1722 value = (value << 8) | lane; 1723 } 1724 1725 tegra_sor_writel(sor, value, SOR_DP_TPG); 1726 1727 err = tegra_sor_dp_train_fast(sor, &link); 1728 if (err < 0) 1729 dev_err(sor->dev, "DP fast link training failed: %d\n", err); 1730 1731 dev_dbg(sor->dev, "fast link training succeeded\n"); 1732 1733 err = tegra_sor_power_up(sor, 250); 1734 if (err < 0) 1735 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 1736 1737 /* CSTM (LVDS, link A/B, upper) */ 1738 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 1739 SOR_CSTM_UPPER; 1740 tegra_sor_writel(sor, value, SOR_CSTM); 1741 1742 /* use DP-A protocol */ 1743 value = tegra_sor_readl(sor, SOR_STATE1); 1744 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 1745 value |= SOR_STATE_ASY_PROTOCOL_DP_A; 1746 tegra_sor_writel(sor, value, SOR_STATE1); 1747 1748 tegra_sor_mode_set(sor, mode, state); 1749 1750 /* PWM setup */ 1751 err = tegra_sor_setup_pwm(sor, 250); 1752 if (err < 0) 1753 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 1754 1755 tegra_sor_update(sor); 1756 1757 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1758 value |= SOR_ENABLE; 1759 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1760 1761 tegra_dc_commit(dc); 1762 1763 err = tegra_sor_attach(sor); 1764 if (err < 0) 1765 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 1766 1767 err = tegra_sor_wakeup(sor); 1768 if (err < 0) 1769 dev_err(sor->dev, "failed to enable DC: %d\n", err); 1770 1771 if (output->panel) 1772 drm_panel_enable(output->panel); 1773 } 1774 1775 static int 1776 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, 1777 struct drm_crtc_state *crtc_state, 1778 struct drm_connector_state *conn_state) 1779 { 1780 struct tegra_output *output = encoder_to_output(encoder); 1781 struct tegra_sor_state *state = to_sor_state(conn_state); 1782 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 1783 unsigned long pclk = crtc_state->mode.clock * 1000; 1784 struct tegra_sor *sor = to_sor(output); 1785 struct drm_display_info *info; 1786 int err; 1787 1788 info = &output->connector.display_info; 1789 1790 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, 1791 pclk, 0); 1792 if (err < 0) { 1793 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1794 return err; 1795 } 1796 1797 switch (info->bpc) { 1798 case 8: 1799 case 6: 1800 state->bpc = info->bpc; 1801 break; 1802 1803 default: 1804 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); 1805 state->bpc = 8; 1806 break; 1807 } 1808 1809 return 0; 1810 } 1811 1812 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = { 1813 .disable = tegra_sor_edp_disable, 1814 .enable = tegra_sor_edp_enable, 1815 .atomic_check = tegra_sor_encoder_atomic_check, 1816 }; 1817 1818 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) 1819 { 1820 u32 value = 0; 1821 size_t i; 1822 1823 for (i = size; i > 0; i--) 1824 value = (value << 8) | ptr[i - 1]; 1825 1826 return value; 1827 } 1828 1829 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, 1830 const void *data, size_t size) 1831 { 1832 const u8 *ptr = data; 1833 unsigned long offset; 1834 size_t i, j; 1835 u32 value; 1836 1837 switch (ptr[0]) { 1838 case HDMI_INFOFRAME_TYPE_AVI: 1839 offset = SOR_HDMI_AVI_INFOFRAME_HEADER; 1840 break; 1841 1842 case HDMI_INFOFRAME_TYPE_AUDIO: 1843 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; 1844 break; 1845 1846 case HDMI_INFOFRAME_TYPE_VENDOR: 1847 offset = SOR_HDMI_VSI_INFOFRAME_HEADER; 1848 break; 1849 1850 default: 1851 dev_err(sor->dev, "unsupported infoframe type: %02x\n", 1852 ptr[0]); 1853 return; 1854 } 1855 1856 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 1857 INFOFRAME_HEADER_VERSION(ptr[1]) | 1858 INFOFRAME_HEADER_LEN(ptr[2]); 1859 tegra_sor_writel(sor, value, offset); 1860 offset++; 1861 1862 /* 1863 * Each subpack contains 7 bytes, divided into: 1864 * - subpack_low: bytes 0 - 3 1865 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 1866 */ 1867 for (i = 3, j = 0; i < size; i += 7, j += 8) { 1868 size_t rem = size - i, num = min_t(size_t, rem, 4); 1869 1870 value = tegra_sor_hdmi_subpack(&ptr[i], num); 1871 tegra_sor_writel(sor, value, offset++); 1872 1873 num = min_t(size_t, rem - num, 3); 1874 1875 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); 1876 tegra_sor_writel(sor, value, offset++); 1877 } 1878 } 1879 1880 static int 1881 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, 1882 const struct drm_display_mode *mode) 1883 { 1884 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 1885 struct hdmi_avi_infoframe frame; 1886 u32 value; 1887 int err; 1888 1889 /* disable AVI infoframe */ 1890 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 1891 value &= ~INFOFRAME_CTRL_SINGLE; 1892 value &= ~INFOFRAME_CTRL_OTHER; 1893 value &= ~INFOFRAME_CTRL_ENABLE; 1894 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 1895 1896 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1897 if (err < 0) { 1898 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 1899 return err; 1900 } 1901 1902 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1903 if (err < 0) { 1904 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); 1905 return err; 1906 } 1907 1908 tegra_sor_hdmi_write_infopack(sor, buffer, err); 1909 1910 /* enable AVI infoframe */ 1911 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 1912 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 1913 value |= INFOFRAME_CTRL_ENABLE; 1914 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 1915 1916 return 0; 1917 } 1918 1919 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) 1920 { 1921 u32 value; 1922 1923 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 1924 value &= ~INFOFRAME_CTRL_ENABLE; 1925 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 1926 } 1927 1928 static struct tegra_sor_hdmi_settings * 1929 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) 1930 { 1931 unsigned int i; 1932 1933 for (i = 0; i < sor->num_settings; i++) 1934 if (frequency <= sor->settings[i].frequency) 1935 return &sor->settings[i]; 1936 1937 return NULL; 1938 } 1939 1940 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) 1941 { 1942 struct tegra_output *output = encoder_to_output(encoder); 1943 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1944 struct tegra_sor *sor = to_sor(output); 1945 u32 value; 1946 int err; 1947 1948 err = tegra_sor_detach(sor); 1949 if (err < 0) 1950 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1951 1952 tegra_sor_writel(sor, 0, SOR_STATE1); 1953 tegra_sor_update(sor); 1954 1955 /* disable display to SOR clock */ 1956 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1957 value &= ~SOR1_TIMING_CYA; 1958 value &= ~SOR1_ENABLE; 1959 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1960 1961 tegra_dc_commit(dc); 1962 1963 err = tegra_sor_power_down(sor); 1964 if (err < 0) 1965 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1966 1967 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI); 1968 if (err < 0) 1969 dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err); 1970 1971 pm_runtime_put(sor->dev); 1972 } 1973 1974 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) 1975 { 1976 struct tegra_output *output = encoder_to_output(encoder); 1977 unsigned int h_ref_to_sync = 1, pulse_start, max_ac; 1978 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1979 struct tegra_sor_hdmi_settings *settings; 1980 struct tegra_sor *sor = to_sor(output); 1981 struct tegra_sor_state *state; 1982 struct drm_display_mode *mode; 1983 unsigned int div; 1984 u32 value; 1985 int err; 1986 1987 state = to_sor_state(output->connector.state); 1988 mode = &encoder->crtc->state->adjusted_mode; 1989 1990 pm_runtime_get_sync(sor->dev); 1991 1992 /* switch to safe parent clock */ 1993 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1994 if (err < 0) 1995 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1996 1997 div = clk_get_rate(sor->clk) / 1000000 * 4; 1998 1999 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI); 2000 if (err < 0) 2001 dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err); 2002 2003 usleep_range(20, 100); 2004 2005 value = tegra_sor_readl(sor, SOR_PLL2); 2006 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2007 tegra_sor_writel(sor, value, SOR_PLL2); 2008 2009 usleep_range(20, 100); 2010 2011 value = tegra_sor_readl(sor, SOR_PLL3); 2012 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; 2013 tegra_sor_writel(sor, value, SOR_PLL3); 2014 2015 value = tegra_sor_readl(sor, SOR_PLL0); 2016 value &= ~SOR_PLL0_VCOPD; 2017 value &= ~SOR_PLL0_PWR; 2018 tegra_sor_writel(sor, value, SOR_PLL0); 2019 2020 value = tegra_sor_readl(sor, SOR_PLL2); 2021 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2022 tegra_sor_writel(sor, value, SOR_PLL2); 2023 2024 usleep_range(200, 400); 2025 2026 value = tegra_sor_readl(sor, SOR_PLL2); 2027 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2028 value &= ~SOR_PLL2_PORT_POWERDOWN; 2029 tegra_sor_writel(sor, value, SOR_PLL2); 2030 2031 usleep_range(20, 100); 2032 2033 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2034 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 2035 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 2036 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2037 2038 while (true) { 2039 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2040 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) 2041 break; 2042 2043 usleep_range(250, 1000); 2044 } 2045 2046 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 2047 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); 2048 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 2049 2050 while (true) { 2051 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2052 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 2053 break; 2054 2055 usleep_range(250, 1000); 2056 } 2057 2058 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2059 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 2060 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2061 2062 if (mode->clock < 340000) 2063 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 2064 else 2065 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; 2066 2067 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 2068 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2069 2070 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2071 value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2072 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2073 value |= SOR_DP_SPARE_SEQ_ENABLE; 2074 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2075 2076 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | 2077 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); 2078 tegra_sor_writel(sor, value, SOR_SEQ_CTL); 2079 2080 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | 2081 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); 2082 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); 2083 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); 2084 2085 /* program the reference clock */ 2086 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); 2087 tegra_sor_writel(sor, value, SOR_REFCLK); 2088 2089 /* XXX don't hardcode */ 2090 value = SOR_XBAR_CTRL_LINK1_XSEL(4, 4) | 2091 SOR_XBAR_CTRL_LINK1_XSEL(3, 3) | 2092 SOR_XBAR_CTRL_LINK1_XSEL(2, 2) | 2093 SOR_XBAR_CTRL_LINK1_XSEL(1, 1) | 2094 SOR_XBAR_CTRL_LINK1_XSEL(0, 0) | 2095 SOR_XBAR_CTRL_LINK0_XSEL(4, 4) | 2096 SOR_XBAR_CTRL_LINK0_XSEL(3, 3) | 2097 SOR_XBAR_CTRL_LINK0_XSEL(2, 0) | 2098 SOR_XBAR_CTRL_LINK0_XSEL(1, 1) | 2099 SOR_XBAR_CTRL_LINK0_XSEL(0, 2); 2100 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2101 2102 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2103 2104 /* switch to parent clock */ 2105 err = clk_set_parent(sor->clk_src, sor->clk_parent); 2106 if (err < 0) 2107 dev_err(sor->dev, "failed to set source clock: %d\n", err); 2108 2109 err = tegra_sor_set_parent_clock(sor, sor->clk_src); 2110 if (err < 0) 2111 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 2112 2113 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2114 2115 /* XXX is this the proper check? */ 2116 if (mode->clock < 75000) 2117 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; 2118 2119 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); 2120 2121 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; 2122 2123 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | 2124 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); 2125 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); 2126 2127 /* H_PULSE2 setup */ 2128 pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) + 2129 (mode->htotal - mode->hsync_end) - 10; 2130 2131 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | 2132 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; 2133 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 2134 2135 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); 2136 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 2137 2138 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); 2139 value |= H_PULSE2_ENABLE; 2140 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); 2141 2142 /* infoframe setup */ 2143 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); 2144 if (err < 0) 2145 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2146 2147 /* XXX HDMI audio support not implemented yet */ 2148 tegra_sor_hdmi_disable_audio_infoframe(sor); 2149 2150 /* use single TMDS protocol */ 2151 value = tegra_sor_readl(sor, SOR_STATE1); 2152 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2153 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; 2154 tegra_sor_writel(sor, value, SOR_STATE1); 2155 2156 /* power up pad calibration */ 2157 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2158 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 2159 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2160 2161 /* production settings */ 2162 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); 2163 if (!settings) { 2164 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", 2165 mode->clock * 1000); 2166 return; 2167 } 2168 2169 value = tegra_sor_readl(sor, SOR_PLL0); 2170 value &= ~SOR_PLL0_ICHPMP_MASK; 2171 value &= ~SOR_PLL0_VCOCAP_MASK; 2172 value |= SOR_PLL0_ICHPMP(settings->ichpmp); 2173 value |= SOR_PLL0_VCOCAP(settings->vcocap); 2174 tegra_sor_writel(sor, value, SOR_PLL0); 2175 2176 tegra_sor_dp_term_calibrate(sor); 2177 2178 value = tegra_sor_readl(sor, SOR_PLL1); 2179 value &= ~SOR_PLL1_LOADADJ_MASK; 2180 value |= SOR_PLL1_LOADADJ(settings->loadadj); 2181 tegra_sor_writel(sor, value, SOR_PLL1); 2182 2183 value = tegra_sor_readl(sor, SOR_PLL3); 2184 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; 2185 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref); 2186 tegra_sor_writel(sor, value, SOR_PLL3); 2187 2188 value = settings->drive_current[0] << 24 | 2189 settings->drive_current[1] << 16 | 2190 settings->drive_current[2] << 8 | 2191 settings->drive_current[3] << 0; 2192 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 2193 2194 value = settings->preemphasis[0] << 24 | 2195 settings->preemphasis[1] << 16 | 2196 settings->preemphasis[2] << 8 | 2197 settings->preemphasis[3] << 0; 2198 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 2199 2200 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2201 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 2202 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 2203 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu); 2204 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2205 2206 /* power down pad calibration */ 2207 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 2208 value |= SOR_DP_PADCTL_PAD_CAL_PD; 2209 tegra_sor_writel(sor, value, SOR_DP_PADCTL0); 2210 2211 /* miscellaneous display controller settings */ 2212 value = VSYNC_H_POSITION(1); 2213 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); 2214 2215 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2216 value &= ~DITHER_CONTROL_MASK; 2217 value &= ~BASE_COLOR_SIZE_MASK; 2218 2219 switch (state->bpc) { 2220 case 6: 2221 value |= BASE_COLOR_SIZE_666; 2222 break; 2223 2224 case 8: 2225 value |= BASE_COLOR_SIZE_888; 2226 break; 2227 2228 default: 2229 WARN(1, "%u bits-per-color not supported\n", state->bpc); 2230 value |= BASE_COLOR_SIZE_888; 2231 break; 2232 } 2233 2234 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2235 2236 err = tegra_sor_power_up(sor, 250); 2237 if (err < 0) 2238 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2239 2240 /* configure dynamic range of output */ 2241 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); 2242 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; 2243 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; 2244 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); 2245 2246 /* configure colorspace */ 2247 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe)); 2248 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; 2249 value |= SOR_HEAD_STATE_COLORSPACE_RGB; 2250 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe)); 2251 2252 tegra_sor_mode_set(sor, mode, state); 2253 2254 tegra_sor_update(sor); 2255 2256 err = tegra_sor_attach(sor); 2257 if (err < 0) 2258 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2259 2260 /* enable display to SOR clock and generate HDMI preamble */ 2261 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2262 value |= SOR1_ENABLE | SOR1_TIMING_CYA; 2263 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2264 2265 tegra_dc_commit(dc); 2266 2267 err = tegra_sor_wakeup(sor); 2268 if (err < 0) 2269 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2270 } 2271 2272 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { 2273 .disable = tegra_sor_hdmi_disable, 2274 .enable = tegra_sor_hdmi_enable, 2275 .atomic_check = tegra_sor_encoder_atomic_check, 2276 }; 2277 2278 static int tegra_sor_init(struct host1x_client *client) 2279 { 2280 struct drm_device *drm = dev_get_drvdata(client->parent); 2281 const struct drm_encoder_helper_funcs *helpers = NULL; 2282 struct tegra_sor *sor = host1x_client_to_sor(client); 2283 int connector = DRM_MODE_CONNECTOR_Unknown; 2284 int encoder = DRM_MODE_ENCODER_NONE; 2285 int err; 2286 2287 if (!sor->aux) { 2288 if (sor->soc->supports_hdmi) { 2289 connector = DRM_MODE_CONNECTOR_HDMIA; 2290 encoder = DRM_MODE_ENCODER_TMDS; 2291 helpers = &tegra_sor_hdmi_helpers; 2292 } else if (sor->soc->supports_lvds) { 2293 connector = DRM_MODE_CONNECTOR_LVDS; 2294 encoder = DRM_MODE_ENCODER_LVDS; 2295 } 2296 } else { 2297 if (sor->soc->supports_edp) { 2298 connector = DRM_MODE_CONNECTOR_eDP; 2299 encoder = DRM_MODE_ENCODER_TMDS; 2300 helpers = &tegra_sor_edp_helpers; 2301 } else if (sor->soc->supports_dp) { 2302 connector = DRM_MODE_CONNECTOR_DisplayPort; 2303 encoder = DRM_MODE_ENCODER_TMDS; 2304 } 2305 } 2306 2307 sor->output.dev = sor->dev; 2308 2309 drm_connector_init(drm, &sor->output.connector, 2310 &tegra_sor_connector_funcs, 2311 connector); 2312 drm_connector_helper_add(&sor->output.connector, 2313 &tegra_sor_connector_helper_funcs); 2314 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; 2315 2316 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, 2317 encoder, NULL); 2318 drm_encoder_helper_add(&sor->output.encoder, helpers); 2319 2320 drm_mode_connector_attach_encoder(&sor->output.connector, 2321 &sor->output.encoder); 2322 drm_connector_register(&sor->output.connector); 2323 2324 err = tegra_output_init(drm, &sor->output); 2325 if (err < 0) { 2326 dev_err(client->dev, "failed to initialize output: %d\n", err); 2327 return err; 2328 } 2329 2330 sor->output.encoder.possible_crtcs = 0x3; 2331 2332 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 2333 err = tegra_sor_debugfs_init(sor, drm->primary); 2334 if (err < 0) 2335 dev_err(sor->dev, "debugfs setup failed: %d\n", err); 2336 } 2337 2338 if (sor->aux) { 2339 err = drm_dp_aux_attach(sor->aux, &sor->output); 2340 if (err < 0) { 2341 dev_err(sor->dev, "failed to attach DP: %d\n", err); 2342 return err; 2343 } 2344 } 2345 2346 /* 2347 * XXX: Remove this reset once proper hand-over from firmware to 2348 * kernel is possible. 2349 */ 2350 err = reset_control_assert(sor->rst); 2351 if (err < 0) { 2352 dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); 2353 return err; 2354 } 2355 2356 err = clk_prepare_enable(sor->clk); 2357 if (err < 0) { 2358 dev_err(sor->dev, "failed to enable clock: %d\n", err); 2359 return err; 2360 } 2361 2362 usleep_range(1000, 3000); 2363 2364 err = reset_control_deassert(sor->rst); 2365 if (err < 0) { 2366 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); 2367 return err; 2368 } 2369 2370 err = clk_prepare_enable(sor->clk_safe); 2371 if (err < 0) 2372 return err; 2373 2374 err = clk_prepare_enable(sor->clk_dp); 2375 if (err < 0) 2376 return err; 2377 2378 return 0; 2379 } 2380 2381 static int tegra_sor_exit(struct host1x_client *client) 2382 { 2383 struct tegra_sor *sor = host1x_client_to_sor(client); 2384 int err; 2385 2386 tegra_output_exit(&sor->output); 2387 2388 if (sor->aux) { 2389 err = drm_dp_aux_detach(sor->aux); 2390 if (err < 0) { 2391 dev_err(sor->dev, "failed to detach DP: %d\n", err); 2392 return err; 2393 } 2394 } 2395 2396 clk_disable_unprepare(sor->clk_safe); 2397 clk_disable_unprepare(sor->clk_dp); 2398 clk_disable_unprepare(sor->clk); 2399 2400 if (IS_ENABLED(CONFIG_DEBUG_FS)) 2401 tegra_sor_debugfs_exit(sor); 2402 2403 return 0; 2404 } 2405 2406 static const struct host1x_client_ops sor_client_ops = { 2407 .init = tegra_sor_init, 2408 .exit = tegra_sor_exit, 2409 }; 2410 2411 static const struct tegra_sor_ops tegra_sor_edp_ops = { 2412 .name = "eDP", 2413 }; 2414 2415 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) 2416 { 2417 int err; 2418 2419 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); 2420 if (IS_ERR(sor->avdd_io_supply)) { 2421 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", 2422 PTR_ERR(sor->avdd_io_supply)); 2423 return PTR_ERR(sor->avdd_io_supply); 2424 } 2425 2426 err = regulator_enable(sor->avdd_io_supply); 2427 if (err < 0) { 2428 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", 2429 err); 2430 return err; 2431 } 2432 2433 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); 2434 if (IS_ERR(sor->vdd_pll_supply)) { 2435 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", 2436 PTR_ERR(sor->vdd_pll_supply)); 2437 return PTR_ERR(sor->vdd_pll_supply); 2438 } 2439 2440 err = regulator_enable(sor->vdd_pll_supply); 2441 if (err < 0) { 2442 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", 2443 err); 2444 return err; 2445 } 2446 2447 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); 2448 if (IS_ERR(sor->hdmi_supply)) { 2449 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", 2450 PTR_ERR(sor->hdmi_supply)); 2451 return PTR_ERR(sor->hdmi_supply); 2452 } 2453 2454 err = regulator_enable(sor->hdmi_supply); 2455 if (err < 0) { 2456 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); 2457 return err; 2458 } 2459 2460 return 0; 2461 } 2462 2463 static int tegra_sor_hdmi_remove(struct tegra_sor *sor) 2464 { 2465 regulator_disable(sor->hdmi_supply); 2466 regulator_disable(sor->vdd_pll_supply); 2467 regulator_disable(sor->avdd_io_supply); 2468 2469 return 0; 2470 } 2471 2472 static const struct tegra_sor_ops tegra_sor_hdmi_ops = { 2473 .name = "HDMI", 2474 .probe = tegra_sor_hdmi_probe, 2475 .remove = tegra_sor_hdmi_remove, 2476 }; 2477 2478 static const struct tegra_sor_soc tegra124_sor = { 2479 .supports_edp = true, 2480 .supports_lvds = true, 2481 .supports_hdmi = false, 2482 .supports_dp = false, 2483 }; 2484 2485 static const struct tegra_sor_soc tegra210_sor = { 2486 .supports_edp = true, 2487 .supports_lvds = false, 2488 .supports_hdmi = false, 2489 .supports_dp = false, 2490 }; 2491 2492 static const struct tegra_sor_soc tegra210_sor1 = { 2493 .supports_edp = false, 2494 .supports_lvds = false, 2495 .supports_hdmi = true, 2496 .supports_dp = true, 2497 2498 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), 2499 .settings = tegra210_sor_hdmi_defaults, 2500 }; 2501 2502 static const struct of_device_id tegra_sor_of_match[] = { 2503 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, 2504 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, 2505 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, 2506 { }, 2507 }; 2508 MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 2509 2510 static int tegra_sor_probe(struct platform_device *pdev) 2511 { 2512 const struct of_device_id *match; 2513 struct device_node *np; 2514 struct tegra_sor *sor; 2515 struct resource *regs; 2516 int err; 2517 2518 match = of_match_device(tegra_sor_of_match, &pdev->dev); 2519 2520 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 2521 if (!sor) 2522 return -ENOMEM; 2523 2524 sor->output.dev = sor->dev = &pdev->dev; 2525 sor->soc = match->data; 2526 2527 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, 2528 sor->soc->num_settings * 2529 sizeof(*sor->settings), 2530 GFP_KERNEL); 2531 if (!sor->settings) 2532 return -ENOMEM; 2533 2534 sor->num_settings = sor->soc->num_settings; 2535 2536 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 2537 if (np) { 2538 sor->aux = drm_dp_aux_find_by_of_node(np); 2539 of_node_put(np); 2540 2541 if (!sor->aux) 2542 return -EPROBE_DEFER; 2543 } 2544 2545 if (!sor->aux) { 2546 if (sor->soc->supports_hdmi) { 2547 sor->ops = &tegra_sor_hdmi_ops; 2548 } else if (sor->soc->supports_lvds) { 2549 dev_err(&pdev->dev, "LVDS not supported yet\n"); 2550 return -ENODEV; 2551 } else { 2552 dev_err(&pdev->dev, "unknown (non-DP) support\n"); 2553 return -ENODEV; 2554 } 2555 } else { 2556 if (sor->soc->supports_edp) { 2557 sor->ops = &tegra_sor_edp_ops; 2558 } else if (sor->soc->supports_dp) { 2559 dev_err(&pdev->dev, "DisplayPort not supported yet\n"); 2560 return -ENODEV; 2561 } else { 2562 dev_err(&pdev->dev, "unknown (DP) support\n"); 2563 return -ENODEV; 2564 } 2565 } 2566 2567 err = tegra_output_probe(&sor->output); 2568 if (err < 0) { 2569 dev_err(&pdev->dev, "failed to probe output: %d\n", err); 2570 return err; 2571 } 2572 2573 if (sor->ops && sor->ops->probe) { 2574 err = sor->ops->probe(sor); 2575 if (err < 0) { 2576 dev_err(&pdev->dev, "failed to probe %s: %d\n", 2577 sor->ops->name, err); 2578 goto output; 2579 } 2580 } 2581 2582 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2583 sor->regs = devm_ioremap_resource(&pdev->dev, regs); 2584 if (IS_ERR(sor->regs)) { 2585 err = PTR_ERR(sor->regs); 2586 goto remove; 2587 } 2588 2589 sor->rst = devm_reset_control_get(&pdev->dev, "sor"); 2590 if (IS_ERR(sor->rst)) { 2591 err = PTR_ERR(sor->rst); 2592 dev_err(&pdev->dev, "failed to get reset control: %d\n", err); 2593 goto remove; 2594 } 2595 2596 sor->clk = devm_clk_get(&pdev->dev, NULL); 2597 if (IS_ERR(sor->clk)) { 2598 err = PTR_ERR(sor->clk); 2599 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); 2600 goto remove; 2601 } 2602 2603 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { 2604 sor->clk_src = devm_clk_get(&pdev->dev, "source"); 2605 if (IS_ERR(sor->clk_src)) { 2606 err = PTR_ERR(sor->clk_src); 2607 dev_err(sor->dev, "failed to get source clock: %d\n", 2608 err); 2609 goto remove; 2610 } 2611 } 2612 2613 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 2614 if (IS_ERR(sor->clk_parent)) { 2615 err = PTR_ERR(sor->clk_parent); 2616 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); 2617 goto remove; 2618 } 2619 2620 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 2621 if (IS_ERR(sor->clk_safe)) { 2622 err = PTR_ERR(sor->clk_safe); 2623 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); 2624 goto remove; 2625 } 2626 2627 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 2628 if (IS_ERR(sor->clk_dp)) { 2629 err = PTR_ERR(sor->clk_dp); 2630 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); 2631 goto remove; 2632 } 2633 2634 platform_set_drvdata(pdev, sor); 2635 pm_runtime_enable(&pdev->dev); 2636 2637 pm_runtime_get_sync(&pdev->dev); 2638 sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick"); 2639 pm_runtime_put(&pdev->dev); 2640 2641 if (IS_ERR(sor->clk_brick)) { 2642 err = PTR_ERR(sor->clk_brick); 2643 dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err); 2644 goto remove; 2645 } 2646 2647 INIT_LIST_HEAD(&sor->client.list); 2648 sor->client.ops = &sor_client_ops; 2649 sor->client.dev = &pdev->dev; 2650 2651 err = host1x_client_register(&sor->client); 2652 if (err < 0) { 2653 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 2654 err); 2655 goto remove; 2656 } 2657 2658 return 0; 2659 2660 remove: 2661 if (sor->ops && sor->ops->remove) 2662 sor->ops->remove(sor); 2663 output: 2664 tegra_output_remove(&sor->output); 2665 return err; 2666 } 2667 2668 static int tegra_sor_remove(struct platform_device *pdev) 2669 { 2670 struct tegra_sor *sor = platform_get_drvdata(pdev); 2671 int err; 2672 2673 pm_runtime_disable(&pdev->dev); 2674 2675 err = host1x_client_unregister(&sor->client); 2676 if (err < 0) { 2677 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 2678 err); 2679 return err; 2680 } 2681 2682 if (sor->ops && sor->ops->remove) { 2683 err = sor->ops->remove(sor); 2684 if (err < 0) 2685 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err); 2686 } 2687 2688 tegra_output_remove(&sor->output); 2689 2690 return 0; 2691 } 2692 2693 #ifdef CONFIG_PM 2694 static int tegra_sor_suspend(struct device *dev) 2695 { 2696 struct tegra_sor *sor = dev_get_drvdata(dev); 2697 int err; 2698 2699 err = reset_control_assert(sor->rst); 2700 if (err < 0) { 2701 dev_err(dev, "failed to assert reset: %d\n", err); 2702 return err; 2703 } 2704 2705 usleep_range(1000, 2000); 2706 2707 clk_disable_unprepare(sor->clk); 2708 2709 return 0; 2710 } 2711 2712 static int tegra_sor_resume(struct device *dev) 2713 { 2714 struct tegra_sor *sor = dev_get_drvdata(dev); 2715 int err; 2716 2717 err = clk_prepare_enable(sor->clk); 2718 if (err < 0) { 2719 dev_err(dev, "failed to enable clock: %d\n", err); 2720 return err; 2721 } 2722 2723 usleep_range(1000, 2000); 2724 2725 err = reset_control_deassert(sor->rst); 2726 if (err < 0) { 2727 dev_err(dev, "failed to deassert reset: %d\n", err); 2728 clk_disable_unprepare(sor->clk); 2729 return err; 2730 } 2731 2732 return 0; 2733 } 2734 #endif 2735 2736 static const struct dev_pm_ops tegra_sor_pm_ops = { 2737 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL) 2738 }; 2739 2740 struct platform_driver tegra_sor_driver = { 2741 .driver = { 2742 .name = "tegra-sor", 2743 .of_match_table = tegra_sor_of_match, 2744 .pm = &tegra_sor_pm_ops, 2745 }, 2746 .probe = tegra_sor_probe, 2747 .remove = tegra_sor_remove, 2748 }; 2749