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Searched refs:reg_data (Results 1 – 25 of 159) sorted by relevance

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/openbmc/linux/drivers/clk/rockchip/
H A Dclk-cpu.c59 const struct rockchip_cpuclk_reg_data *reg_data; member
86 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_recalc_rate() local
87 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]); in rockchip_cpuclk_recalc_rate()
89 clksel0 >>= reg_data->div_core_shift[0]; in rockchip_cpuclk_recalc_rate()
90 clksel0 &= reg_data->div_core_mask[0]; in rockchip_cpuclk_recalc_rate()
155 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_pre_rate_change() local
182 if (alt_div > reg_data->div_core_mask[0]) { in rockchip_cpuclk_pre_rate_change()
184 __func__, alt_div, reg_data->div_core_mask[0]); in rockchip_cpuclk_pre_rate_change()
185 alt_div = reg_data->div_core_mask[0]; in rockchip_cpuclk_pre_rate_change()
198 for (i = 0; i < reg_data->num_cores; i++) { in rockchip_cpuclk_pre_rate_change()
[all …]
/openbmc/linux/drivers/power/supply/
H A Dmax14577_charger.c51 u8 reg_data; in max14577_get_charger_state() local
64 ret = max14577_read_reg(rmap, MAX14577_CHG_REG_CHG_CTRL2, &reg_data); in max14577_get_charger_state()
68 if ((reg_data & CHGCTRL2_MBCHOSTEN_MASK) == 0) { in max14577_get_charger_state()
73 ret = max14577_read_reg(rmap, MAX14577_CHG_REG_STATUS3, &reg_data); in max14577_get_charger_state()
77 if (reg_data & STATUS3_CGMBC_MASK) { in max14577_get_charger_state()
79 if (reg_data & STATUS3_EOC_MASK) in max14577_get_charger_state()
124 u8 reg_data; in max14577_get_online() local
128 ret = max14577_read_reg(rmap, MAX14577_MUIC_REG_STATUS2, &reg_data); in max14577_get_online()
132 reg_data = ((reg_data & STATUS2_CHGTYP_MASK) >> STATUS2_CHGTYP_SHIFT); in max14577_get_online()
133 chg_type = maxim_get_charger_type(chg->max14577->dev_type, reg_data); in max14577_get_online()
[all …]
H A Drt5033_charger.c34 unsigned int reg_data; in rt5033_get_charger_state() local
40 regmap_read(regmap, RT5033_REG_CHG_STAT, &reg_data); in rt5033_get_charger_state()
42 switch (reg_data & RT5033_CHG_STAT_MASK) { in rt5033_get_charger_state()
65 unsigned int reg_data; in rt5033_get_charger_type() local
68 regmap_read(regmap, RT5033_REG_CHG_STAT, &reg_data); in rt5033_get_charger_type()
70 switch (reg_data & RT5033_CHG_STAT_TYPE_MASK) { in rt5033_get_charger_type()
87 unsigned int state, reg_data, data; in rt5033_get_charger_current_limit() local
89 regmap_read(regmap, RT5033_REG_CHG_CTRL5, &reg_data); in rt5033_get_charger_current_limit()
91 state = (reg_data & RT5033_CHGCTRL5_ICHG_MASK) in rt5033_get_charger_current_limit()
103 unsigned int state, reg_data, data; in rt5033_get_charger_const_voltage() local
[all …]
/openbmc/linux/drivers/watchdog/
H A Dmlx_wdt.c59 struct mlxreg_core_data *reg_data; in mlxreg_wdt_check_card_reset() local
69 reg_data = &wdt->pdata->data[wdt->reset_idx]; in mlxreg_wdt_check_card_reset()
70 rc = regmap_read(wdt->regmap, reg_data->reg, &regval); in mlxreg_wdt_check_card_reset()
72 if (regval & ~reg_data->mask) { in mlxreg_wdt_check_card_reset()
83 struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->action_idx]; in mlxreg_wdt_start() local
85 return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask, in mlxreg_wdt_start()
86 BIT(reg_data->bit)); in mlxreg_wdt_start()
92 struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->action_idx]; in mlxreg_wdt_stop() local
94 return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask, in mlxreg_wdt_stop()
95 ~BIT(reg_data->bit)); in mlxreg_wdt_stop()
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/openbmc/linux/drivers/soc/qcom/
H A Dspm.c195 if (drv->reg_data->reg_offset[reg]) in spm_register_write()
197 drv->reg_data->reg_offset[reg]); in spm_register_write()
206 if (!drv->reg_data->reg_offset[reg]) in spm_register_write_sync()
211 drv->reg_data->reg_offset[reg]); in spm_register_write_sync()
213 drv->reg_data->reg_offset[reg]); in spm_register_write_sync()
223 return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); in spm_register_read()
232 start_index = drv->reg_data->start_index[mode]; in spm_set_low_power_mode()
290 drv->reg_data = match_id->data; in spm_dev_probe()
294 addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; in spm_dev_probe()
295 __iowrite32_copy(addr, drv->reg_data->seq, in spm_dev_probe()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A D80003es2lan.c730 u32 reg_data; in e1000_init_hw_80003es2lan() local
776 reg_data = er32(TXDCTL(0)); in e1000_init_hw_80003es2lan()
777 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_80003es2lan()
779 ew32(TXDCTL(0), reg_data); in e1000_init_hw_80003es2lan()
782 reg_data = er32(TXDCTL(1)); in e1000_init_hw_80003es2lan()
783 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_80003es2lan()
785 ew32(TXDCTL(1), reg_data); in e1000_init_hw_80003es2lan()
788 reg_data = er32(TCTL); in e1000_init_hw_80003es2lan()
789 reg_data |= E1000_TCTL_RTLC; in e1000_init_hw_80003es2lan()
790 ew32(TCTL, reg_data); in e1000_init_hw_80003es2lan()
[all …]
/openbmc/linux/drivers/regulator/
H A Dmax14577-regulator.c19 u8 reg_data; in max14577_reg_is_enabled() local
23 max14577_read_reg(rmap, MAX14577_CHG_REG_CHG_CTRL2, &reg_data); in max14577_reg_is_enabled()
24 if ((reg_data & CHGCTRL2_MBCHOSTEN_MASK) == 0) in max14577_reg_is_enabled()
26 max14577_read_reg(rmap, MAX14577_CHG_REG_STATUS3, &reg_data); in max14577_reg_is_enabled()
27 if ((reg_data & STATUS3_CGMBC_MASK) == 0) in max14577_reg_is_enabled()
38 u8 reg_data; in max14577_reg_get_current_limit() local
47 max14577_read_reg(rmap, MAX14577_CHG_REG_CHG_CTRL4, &reg_data); in max14577_reg_get_current_limit()
49 if ((reg_data & CHGCTRL4_MBCICHWRCL_MASK) == 0) in max14577_reg_get_current_limit()
52 reg_data = ((reg_data & CHGCTRL4_MBCICHWRCH_MASK) >> in max14577_reg_get_current_limit()
54 return limits->high_start + reg_data * limits->high_step; in max14577_reg_get_current_limit()
[all …]
H A Dmax77693-regulator.c57 const struct chg_reg_data *reg_data = rdev_get_drvdata(rdev); in max77693_chg_get_current_limit() local
64 ret = regmap_read(rdev->regmap, reg_data->linear_reg, &reg); in max77693_chg_get_current_limit()
68 sel = reg & reg_data->linear_mask; in max77693_chg_get_current_limit()
71 if (sel <= reg_data->min_sel) in max77693_chg_get_current_limit()
74 sel -= reg_data->min_sel; in max77693_chg_get_current_limit()
76 val = chg_min_uA + reg_data->uA_step * sel; in max77693_chg_get_current_limit()
86 const struct chg_reg_data *reg_data = rdev_get_drvdata(rdev); in max77693_chg_set_current_limit() local
90 while (chg_min_uA + reg_data->uA_step * sel < min_uA) in max77693_chg_set_current_limit()
93 if (chg_min_uA + reg_data->uA_step * sel > max_uA) in max77693_chg_set_current_limit()
97 sel += reg_data->min_sel; in max77693_chg_set_current_limit()
[all …]
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_core.h98 u32 reg_data; in reg_set_silent() local
100 reg_data = readl(addr); in reg_set_silent()
101 reg_data &= ~mask; in reg_set_silent()
102 reg_data |= data; in reg_set_silent()
103 writel(reg_data, addr); in reg_set_silent()
117 u16 reg_data; in reg_set_silent16() local
119 reg_data = readw(addr); in reg_set_silent16()
120 reg_data &= ~mask; in reg_set_silent16()
121 reg_data |= data; in reg_set_silent16()
122 writew(reg_data, addr); in reg_set_silent16()
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dseq_exec.c32 u32 unit_base_reg, unit_offset, data, mask, reg_data, reg_addr; in write_op_execute() local
54 reg_data = reg_read(reg_addr); in write_op_execute()
55 reg_data &= (~mask); in write_op_execute()
59 reg_data |= data; in write_op_execute()
60 reg_write(reg_addr, reg_data); in write_op_execute()
63 printf(" - 0x%x\n", reg_data); in write_op_execute()
87 u32 reg_addr, reg_data; in poll_op_execute() local
113 reg_data = reg_read(reg_addr) & mask; in poll_op_execute()
116 } while ((reg_data != data) && (poll_counter < num_of_loops)); in poll_op_execute()
118 if ((poll_counter >= num_of_loops) && (reg_data != data)) { in poll_op_execute()
H A Dhigh_speed_env_spec.c1564 u32 reg_data; in serdes_pex_usb3_pipe_delay_w_a() local
1568 reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG); in serdes_pex_usb3_pipe_delay_w_a()
1578 reg_data |= 1 << (7 + (serdes_num - 3)); in serdes_pex_usb3_pipe_delay_w_a()
1581 reg_data &= ~(1 << (7 + (serdes_num - 3))); in serdes_pex_usb3_pipe_delay_w_a()
1583 reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data); in serdes_pex_usb3_pipe_delay_w_a()
1682 u32 reg_data; in serdes_power_up_ctrl() local
1724 reg_data = reg_read(SOC_CONTROL_REG1); in serdes_power_up_ctrl()
1726 reg_data |= 0x4000; in serdes_power_up_ctrl()
1728 reg_data &= ~0x4000; in serdes_power_up_ctrl()
1729 reg_write(SOC_CONTROL_REG1, reg_data); in serdes_power_up_ctrl()
[all …]
/openbmc/u-boot/drivers/net/pfe_eth/
H A Dpfe_mdio.c22 u32 reg_data; in pfe_write_addr() local
28 reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr); in pfe_write_addr()
30 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_write_addr()
56 u32 reg_data; in pfe_phy_read() local
72 reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | in pfe_phy_read()
75 reg_data = (EMAC_MII_DATA_OP_CL45_RD | EMAC_MII_DATA_TA | in pfe_phy_read()
78 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
111 u32 reg_data; in pfe_phy_write() local
127 reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | in pfe_phy_write()
130 reg_data = (EMAC_MII_DATA_OP_CL45_WR | EMAC_MII_DATA_TA | in pfe_phy_write()
[all …]
/openbmc/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_emaclite.c152 u32 reg_data; in xemaclite_enable_interrupts() local
155 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()
156 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK, in xemaclite_enable_interrupts()
175 u32 reg_data; in xemaclite_disable_interrupts() local
181 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_disable_interrupts()
182 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), in xemaclite_disable_interrupts()
186 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET); in xemaclite_disable_interrupts()
187 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), in xemaclite_disable_interrupts()
310 u32 reg_data; in xemaclite_send_data() local
321 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
[all …]
/openbmc/linux/drivers/usb/isp1760/
H A Disp1760-if.c39 u32 reg_data; in isp1761_pci_init() local
75 reg_data = 0; in isp1761_pci_init()
76 while ((reg_data != 0xFACE) && retry_count) { in isp1761_pci_init()
82 reg_data = readl(iobase + ISP176x_HC_SCRATCH) & 0x0000ffff; in isp1761_pci_init()
92 if (reg_data != 0xFACE) { in isp1761_pci_init()
93 dev_err(&dev->dev, "scratch register mismatch %x\n", reg_data); in isp1761_pci_init()
115 reg_data = readl(iobase + PLX_INT_CSR_REG); in isp1761_pci_init()
116 reg_data |= 0x900; in isp1761_pci_init()
117 writel(reg_data, iobase + PLX_INT_CSR_REG); in isp1761_pci_init()
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/
H A Ddbg.c1026 struct iwl_dump_ini_region_data *reg_data, in iwl_dump_ini_prph_mac_iter() argument
1029 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; in iwl_dump_ini_prph_mac_iter()
1051 struct iwl_dump_ini_region_data *reg_data, in iwl_dump_ini_prph_phy_iter() argument
1054 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; in iwl_dump_ini_prph_phy_iter()
1101 struct iwl_dump_ini_region_data *reg_data, in iwl_dump_ini_csr_iter() argument
1104 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; in iwl_dump_ini_csr_iter()
1120 struct iwl_dump_ini_region_data *reg_data, in iwl_dump_ini_config_iter() argument
1124 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; in iwl_dump_ini_config_iter()
1152 struct iwl_dump_ini_region_data *reg_data, in iwl_dump_ini_dev_mem_iter() argument
1155 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; in iwl_dump_ini_dev_mem_iter()
[all …]
/openbmc/linux/drivers/char/xilinx_hwicap/
H A Dfifo_icap.c359 u32 reg_data; in fifo_icap_reset() local
364 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_reset()
367 reg_data | XHI_CR_SW_RESET_MASK); in fifo_icap_reset()
370 reg_data & (~XHI_CR_SW_RESET_MASK)); in fifo_icap_reset()
380 u32 reg_data; in fifo_icap_flush_fifo() local
385 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_flush_fifo()
388 reg_data | XHI_CR_FIFO_CLR_MASK); in fifo_icap_flush_fifo()
391 reg_data & (~XHI_CR_FIFO_CLR_MASK)); in fifo_icap_flush_fifo()
/openbmc/u-boot/drivers/gpio/
H A Dbcm6345_gpio.c18 void __iomem *reg_data; member
25 return !!(readl_be(priv->reg_data) & BIT(offset)); in bcm6345_gpio_get_value()
34 setbits_be32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
36 clrbits_be32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
96 priv->reg_data = dev_remap_addr_index(dev, 1); in bcm6345_gpio_probe()
97 if (!priv->reg_data) in bcm6345_gpio_probe()
/openbmc/linux/drivers/clk/ti/
H A Dclkctrl.c514 const struct omap_clkctrl_reg_data *reg_data; in _ti_omap4_clkctrl_setup() local
644 reg_data = data->regs; in _ti_omap4_clkctrl_setup()
646 while (reg_data->parent) { in _ti_omap4_clkctrl_setup()
647 if ((reg_data->flags & CLKF_SOC_MASK) && in _ti_omap4_clkctrl_setup()
648 (reg_data->flags & soc_mask) == 0) { in _ti_omap4_clkctrl_setup()
649 reg_data++; in _ti_omap4_clkctrl_setup()
657 hw->enable_reg.ptr = provider->base + reg_data->offset; in _ti_omap4_clkctrl_setup()
659 _ti_clkctrl_setup_subclks(provider, node, reg_data, in _ti_omap4_clkctrl_setup()
662 if (reg_data->flags & CLKF_SW_SUP) in _ti_omap4_clkctrl_setup()
664 if (reg_data->flags & CLKF_HW_SUP) in _ti_omap4_clkctrl_setup()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v2_3.c501 uint32_t reg_data = 0; in nbio_v2_3_apply_lc_spc_mode_wa() local
508 reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); in nbio_v2_3_apply_lc_spc_mode_wa()
509 link_width = (reg_data & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) in nbio_v2_3_apply_lc_spc_mode_wa()
517 reg_data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v2_3_apply_lc_spc_mode_wa()
518 reg_data &= ~PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK; in nbio_v2_3_apply_lc_spc_mode_wa()
519 reg_data |= (0x2 << PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT); in nbio_v2_3_apply_lc_spc_mode_wa()
520 WREG32_PCIE(smnPCIE_LC_CNTL6, reg_data); in nbio_v2_3_apply_lc_spc_mode_wa()
526 uint32_t reg_data = 0; in nbio_v2_3_apply_l1_link_width_reconfig_wa() local
531 reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); in nbio_v2_3_apply_l1_link_width_reconfig_wa()
532 reg_data |= PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK; in nbio_v2_3_apply_l1_link_width_reconfig_wa()
[all …]
/openbmc/linux/drivers/extcon/
H A Dextcon-ptn5150.c74 unsigned int port_status, reg_data, vbus; in ptn5150_check_state() local
78 ret = regmap_read(info->regmap, PTN5150_REG_CC_STATUS, &reg_data); in ptn5150_check_state()
84 port_status = FIELD_GET(PTN5150_REG_CC_PORT_ATTACHMENT, reg_data); in ptn5150_check_state()
95 vbus = FIELD_GET(PTN5150_REG_CC_VBUS_DETECTION, reg_data); in ptn5150_check_state()
183 unsigned int reg_data, vendor_id, version_id; in ptn5150_init_dev_type() local
186 ret = regmap_read(info->regmap, PTN5150_REG_DEVICE_ID, &reg_data); in ptn5150_init_dev_type()
192 vendor_id = FIELD_GET(PTN5150_REG_DEVICE_ID_VENDOR, reg_data); in ptn5150_init_dev_type()
193 version_id = FIELD_GET(PTN5150_REG_DEVICE_ID_VERSION, reg_data); in ptn5150_init_dev_type()
198 ret = regmap_read(info->regmap, PTN5150_REG_INT_STATUS, &reg_data); in ptn5150_init_dev_type()
206 ret = regmap_read(info->regmap, PTN5150_REG_INT_REG_STATUS, &reg_data); in ptn5150_init_dev_type()
H A Dextcon-sm5502.c30 struct reg_data { struct
66 struct reg_data *reg_data; member
74 static struct reg_data sm5502_reg_data[] = {
102 static struct reg_data sm5504_reg_data[] = {
644 unsigned int reg_data, vendor_id, version_id; in sm5502_init_dev_type() local
648 ret = regmap_read(info->regmap, SM5502_REG_DEVICE_ID, &reg_data); in sm5502_init_dev_type()
655 vendor_id = ((reg_data & SM5502_REG_DEVICE_ID_VENDOR_MASK) >> in sm5502_init_dev_type()
657 version_id = ((reg_data & SM5502_REG_DEVICE_ID_VERSION_MASK) >> in sm5502_init_dev_type()
667 if (!info->type->reg_data[i].invert) in sm5502_init_dev_type()
668 val |= ~info->type->reg_data[i].val; in sm5502_init_dev_type()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dmt6660.c49 u8 reg_data[4]; in mt6660_reg_write() local
53 reg_data[size - i - 1] = (val >> (8 * i)) & 0xff; in mt6660_reg_write()
55 return i2c_smbus_write_i2c_block_data(chip->i2c, reg, size, reg_data); in mt6660_reg_write()
64 u32 reg_data = 0; in mt6660_reg_read() local
70 reg_data <<= 8; in mt6660_reg_read()
71 reg_data |= data[i]; in mt6660_reg_read()
73 *val = reg_data; in mt6660_reg_read()
334 u16 reg_data = 0; in mt6660_component_aif_hw_params() local
347 reg_data = 3; in mt6660_component_aif_hw_params()
350 reg_data = 2; in mt6660_component_aif_hw_params()
[all …]
/openbmc/linux/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_mbox.c50 u32 reg_data; in send_mbox_write_cmd() local
63 reg_data = BIT_ULL(MBOX_BUSY_BIT) | id; in send_mbox_write_cmd()
64 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_write_cmd()
76 u32 reg_data; in send_mbox_read_cmd() local
88 reg_data = BIT_ULL(MBOX_BUSY_BIT) | id; in send_mbox_read_cmd()
89 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_read_cmd()
/openbmc/linux/drivers/staging/vt6656/
H A Drf.c198 u8 reg_data[4]; in vnt_rf_write_embedded() local
202 reg_data[0] = (u8)data; in vnt_rf_write_embedded()
203 reg_data[1] = (u8)(data >> 8); in vnt_rf_write_embedded()
204 reg_data[2] = (u8)(data >> 16); in vnt_rf_write_embedded()
205 reg_data[3] = (u8)(data >> 24); in vnt_rf_write_embedded()
208 ARRAY_SIZE(reg_data), reg_data); in vnt_rf_write_embedded()
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_debug.c514 u32 reg_data; in ddr3_tip_print_stability_log() local
572 csindex, &reg_data); in ddr3_tip_print_stability_log()
573 printf("%d,%d,", (reg_data & 0x1f), in ddr3_tip_print_stability_log()
574 ((reg_data & 0x3e0) >> 5)); in ddr3_tip_print_stability_log()
580 &reg_data); in ddr3_tip_print_stability_log()
582 (reg_data & 0x1f) + in ddr3_tip_print_stability_log()
583 ((reg_data & 0x1c0) >> 6) * 32, in ddr3_tip_print_stability_log()
584 (reg_data & 0x1f), in ddr3_tip_print_stability_log()
585 (reg_data & 0x1c0) >> 6); in ddr3_tip_print_stability_log()
600 &reg_data); in ddr3_tip_print_stability_log()
[all …]

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