183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2f1df9364SStefan Roese /* 3f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4f1df9364SStefan Roese */ 5f1df9364SStefan Roese 6f1df9364SStefan Roese #ifndef _DDR3_TRAINING_IP_DEF_H 7f1df9364SStefan Roese #define _DDR3_TRAINING_IP_DEF_H 8f1df9364SStefan Roese 9f1df9364SStefan Roese #define PATTERN_55 0x55555555 10f1df9364SStefan Roese #define PATTERN_AA 0xaaaaaaaa 11f1df9364SStefan Roese #define PATTERN_80 0x80808080 12f1df9364SStefan Roese #define PATTERN_20 0x20202020 13f1df9364SStefan Roese #define PATTERN_01 0x01010101 14f1df9364SStefan Roese #define PATTERN_FF 0xffffffff 15f1df9364SStefan Roese #define PATTERN_00 0x00000000 16f1df9364SStefan Roese 17f1df9364SStefan Roese /* 16bit bus width patterns */ 18f1df9364SStefan Roese #define PATTERN_55AA 0x5555aaaa 19f1df9364SStefan Roese #define PATTERN_00FF 0x0000ffff 20f1df9364SStefan Roese #define PATTERN_0080 0x00008080 21f1df9364SStefan Roese 22f1df9364SStefan Roese #define INVALID_VALUE 0xffffffff 23f1df9364SStefan Roese #define MAX_NUM_OF_DUNITS 32 24f1df9364SStefan Roese /* 25f1df9364SStefan Roese * length *2 = length in words of pattern, first low address, 26f1df9364SStefan Roese * second high address 27f1df9364SStefan Roese */ 28f1df9364SStefan Roese #define TEST_PATTERN_LENGTH 4 29f1df9364SStefan Roese #define KILLER_PATTERN_DQ_NUMBER 8 30f1df9364SStefan Roese #define SSO_DQ_NUMBER 4 31f1df9364SStefan Roese #define PATTERN_MAXIMUM_LENGTH 64 32f1df9364SStefan Roese #define ADLL_TX_LENGTH 64 33f1df9364SStefan Roese #define ADLL_RX_LENGTH 32 34f1df9364SStefan Roese 35f1df9364SStefan Roese #define PARAM_NOT_CARE 0 36*2b4ffbf6SChris Packham #define PARAM_UNDEFINED 0xffffffff 37f1df9364SStefan Roese 38f1df9364SStefan Roese #define READ_LEVELING_PHY_OFFSET 2 39f1df9364SStefan Roese #define WRITE_LEVELING_PHY_OFFSET 0 40f1df9364SStefan Roese 41f1df9364SStefan Roese #define MASK_ALL_BITS 0xffffffff 42f1df9364SStefan Roese 43f1df9364SStefan Roese #define CS_BIT_MASK 0xf 44f1df9364SStefan Roese 45f1df9364SStefan Roese /* DFX access */ 46f1df9364SStefan Roese #define BROADCAST_ID 28 47f1df9364SStefan Roese #define MULTICAST_ID 29 48f1df9364SStefan Roese 49f1df9364SStefan Roese #define XSB_BASE_ADDR 0x00004000 50f1df9364SStefan Roese #define XSB_CTRL_0_REG 0x00000000 51f1df9364SStefan Roese #define XSB_CTRL_1_REG 0x00000004 52f1df9364SStefan Roese #define XSB_CMD_REG 0x00000008 53f1df9364SStefan Roese #define XSB_ADDRESS_REG 0x0000000c 54f1df9364SStefan Roese #define XSB_DATA_REG 0x00000010 55f1df9364SStefan Roese #define PIPE_ENABLE_ADDR 0x000f8000 56f1df9364SStefan Roese #define ENABLE_DDR_TUNING_ADDR 0x000f829c 57f1df9364SStefan Roese 58f1df9364SStefan Roese #define CLIENT_BASE_ADDR 0x00002000 59f1df9364SStefan Roese #define CLIENT_CTRL_REG 0x00000000 60f1df9364SStefan Roese 61f1df9364SStefan Roese #define TARGET_INT 0x1801 62f1df9364SStefan Roese #define TARGET_EXT 0x180e 63f1df9364SStefan Roese #define BYTE_EN 0 64f1df9364SStefan Roese #define CMD_READ 0 65f1df9364SStefan Roese #define CMD_WRITE 1 66f1df9364SStefan Roese 67f1df9364SStefan Roese #define INTERNAL_ACCESS_PORT 1 68f1df9364SStefan Roese #define EXECUTING 1 69f1df9364SStefan Roese #define ACCESS_EXT 1 70f1df9364SStefan Roese #define CS2_EXIST_BIT 2 71f1df9364SStefan Roese #define TRAINING_ID 0xf 72f1df9364SStefan Roese #define EXT_TRAINING_ID 1 73f1df9364SStefan Roese #define EXT_MODE 0x4 74f1df9364SStefan Roese 75f1df9364SStefan Roese #define GET_RESULT_STATE(res) (res) 76f1df9364SStefan Roese #define SET_RESULT_STATE(res, state) (res = state) 77f1df9364SStefan Roese 78f1df9364SStefan Roese #define ADDR_SIZE_512MB 0x04000000 79f1df9364SStefan Roese #define ADDR_SIZE_1GB 0x08000000 80f1df9364SStefan Roese #define ADDR_SIZE_2GB 0x10000000 81f1df9364SStefan Roese #define ADDR_SIZE_4GB 0x20000000 82f1df9364SStefan Roese #define ADDR_SIZE_8GB 0x40000000 83f1df9364SStefan Roese 84f1df9364SStefan Roese enum hws_edge_compare { 85f1df9364SStefan Roese EDGE_PF, 86f1df9364SStefan Roese EDGE_FP, 87f1df9364SStefan Roese EDGE_FPF, 88f1df9364SStefan Roese EDGE_PFP 89f1df9364SStefan Roese }; 90f1df9364SStefan Roese 91f1df9364SStefan Roese enum hws_control_element { 92f1df9364SStefan Roese HWS_CONTROL_ELEMENT_ADLL, /* per bit 1 edge */ 93f1df9364SStefan Roese HWS_CONTROL_ELEMENT_DQ_SKEW, 94f1df9364SStefan Roese HWS_CONTROL_ELEMENT_DQS_SKEW 95f1df9364SStefan Roese }; 96f1df9364SStefan Roese 97f1df9364SStefan Roese enum hws_search_dir { 98f1df9364SStefan Roese HWS_LOW2HIGH, 99f1df9364SStefan Roese HWS_HIGH2LOW, 100f1df9364SStefan Roese HWS_SEARCH_DIR_LIMIT 101f1df9364SStefan Roese }; 102f1df9364SStefan Roese 103f1df9364SStefan Roese enum hws_operation { 104f1df9364SStefan Roese OPERATION_READ = 0, 105f1df9364SStefan Roese OPERATION_WRITE = 1 106f1df9364SStefan Roese }; 107f1df9364SStefan Roese 108f1df9364SStefan Roese enum hws_training_ip_stat { 109f1df9364SStefan Roese HWS_TRAINING_IP_STATUS_FAIL, 110f1df9364SStefan Roese HWS_TRAINING_IP_STATUS_SUCCESS, 111f1df9364SStefan Roese HWS_TRAINING_IP_STATUS_TIMEOUT 112f1df9364SStefan Roese }; 113f1df9364SStefan Roese 114f1df9364SStefan Roese enum hws_ddr_cs { 115f1df9364SStefan Roese CS_SINGLE, 116f1df9364SStefan Roese CS_NON_SINGLE 117f1df9364SStefan Roese }; 118f1df9364SStefan Roese 119f1df9364SStefan Roese enum hws_ddr_phy { 120f1df9364SStefan Roese DDR_PHY_DATA = 0, 121f1df9364SStefan Roese DDR_PHY_CONTROL = 1 122f1df9364SStefan Roese }; 123f1df9364SStefan Roese 124f1df9364SStefan Roese enum hws_dir { 125f1df9364SStefan Roese OPER_WRITE, 126f1df9364SStefan Roese OPER_READ, 127f1df9364SStefan Roese OPER_WRITE_AND_READ 128f1df9364SStefan Roese }; 129f1df9364SStefan Roese 130f1df9364SStefan Roese enum hws_wl_supp { 131f1df9364SStefan Roese PHASE_SHIFT, 132f1df9364SStefan Roese CLOCK_SHIFT, 133f1df9364SStefan Roese ALIGN_SHIFT 134f1df9364SStefan Roese }; 135f1df9364SStefan Roese 136*2b4ffbf6SChris Packham enum mv_ddr_tip_bit_state { 137*2b4ffbf6SChris Packham BIT_LOW_UI, 138*2b4ffbf6SChris Packham BIT_HIGH_UI, 139*2b4ffbf6SChris Packham BIT_SPLIT_IN, 140*2b4ffbf6SChris Packham BIT_SPLIT_OUT, 141*2b4ffbf6SChris Packham BIT_STATE_LAST 142*2b4ffbf6SChris Packham }; 143*2b4ffbf6SChris Packham 144*2b4ffbf6SChris Packham enum mv_ddr_tip_byte_state{ 145*2b4ffbf6SChris Packham BYTE_NOT_DEFINED, 146*2b4ffbf6SChris Packham BYTE_HOMOGENEOUS_LOW = 0x1, 147*2b4ffbf6SChris Packham BYTE_HOMOGENEOUS_HIGH = 0x2, 148*2b4ffbf6SChris Packham BYTE_HOMOGENEOUS_SPLIT_IN = 0x4, 149*2b4ffbf6SChris Packham BYTE_HOMOGENEOUS_SPLIT_OUT = 0x8, 150*2b4ffbf6SChris Packham BYTE_SPLIT_OUT_MIX = 0x10, 151*2b4ffbf6SChris Packham BYTE_STATE_LAST 152*2b4ffbf6SChris Packham }; 153*2b4ffbf6SChris Packham 154f1df9364SStefan Roese struct reg_data { 155*2b4ffbf6SChris Packham unsigned int reg_addr; 156*2b4ffbf6SChris Packham unsigned int reg_data; 157*2b4ffbf6SChris Packham unsigned int reg_mask; 158*2b4ffbf6SChris Packham }; 159*2b4ffbf6SChris Packham 160*2b4ffbf6SChris Packham enum dm_direction { 161*2b4ffbf6SChris Packham DM_DIR_INVERSE, 162*2b4ffbf6SChris Packham DM_DIR_DIRECT 163f1df9364SStefan Roese }; 164f1df9364SStefan Roese 165f1df9364SStefan Roese #endif /* _DDR3_TRAINING_IP_DEF_H */ 166