Searched refs:hclk_div (Results 1 – 11 of 11) sorted by relevance
81 u32 hclk_div; in rkclk_init() local125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()136 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()145 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()146 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()147 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()158 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
82 u32 hclk_div; in rkclk_init() local126 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; in rkclk_init()127 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()137 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()146 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()147 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()148 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()159 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
375 u32 aclk_div, hclk_div, pclk_div, h2p_div; in rkclk_init() local408 hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ); in rkclk_init()409 assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3); in rkclk_init()421 hclk_div << CPU_HCLK_DIV_SHIFT); in rkclk_init()430 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()431 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()432 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()444 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
143 u32 hclk_div; in rkclk_init() local187 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; in rkclk_init()188 assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3); in rkclk_init()198 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()207 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()208 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()209 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()220 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
1098 u32 hclk_div; in rkclk_init() local1121 assert((hclk_div + 1) * PERIHP_HCLK_HZ == in rkclk_init()1122 PERIHP_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()1132 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | in rkclk_init()1141 assert((hclk_div + 1) * PERILP0_HCLK_HZ == in rkclk_init()1142 PERILP0_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()1152 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | in rkclk_init()1157 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; in rkclk_init()1158 assert((hclk_div + 1) * PERILP1_HCLK_HZ == in rkclk_init()1159 GPLL_HZ && (hclk_div < 0x1f)); in rkclk_init()[all …]
424 u32 hclk_div; in rkclk_init() local449 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; in rkclk_init()450 assert((hclk_div + 1) * PD_BUS_HCLK_HZ == in rkclk_init()451 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); in rkclk_init()461 hclk_div << PD_BUS_HCLK_DIV_SHIFT | in rkclk_init()472 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()473 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()474 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()485 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
282 u32 hclk_div; in rkclk_init() local291 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; in rkclk_init()301 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT); in rkclk_init()
61 const uint8_t hclk_div = in get_HCLK() local63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
306 u8 hclk_div = 0x4; /* default value */ in aspeed_g6_spi_hclk_divisor() local329 hclk_div = ((j << 4) | hclk_masks[i]); in aspeed_g6_spi_hclk_divisor()331 return hclk_div; in aspeed_g6_spi_hclk_divisor()512 u32 hclk_div = 0; in aspeed_spi_timing_calibration() local595 hclk_div = aspeed_g6_spi_hclk_divisor(priv, max_freq); in aspeed_spi_timing_calibration()598 reg_val = (reg_val & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div); in aspeed_spi_timing_calibration()603 (flash->ce_ctrl_user & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div); in aspeed_spi_timing_calibration()605 (flash->ce_ctrl_fread & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div); in aspeed_spi_timing_calibration()
728 u32 val, hclk_div; in clk_ddram_enable() local731 hclk_div = val & clk->busy_mask; in clk_ddram_enable()738 if (hclk_div == 0x0 || hclk_div == (BIT(1) | BIT(0))) in clk_ddram_enable()742 clk->enable_mask, hclk_div << 7); in clk_ddram_enable()
806 uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask); in aspeed_smc_dma_calibration() local807 uint32_t hclk_shift = (hclk_div - 1) << 2; in aspeed_smc_dma_calibration()814 if (hclk_div && hclk_div < 6) { in aspeed_smc_dma_calibration()828 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); in aspeed_smc_dma_calibration()