1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
284ad6884SPeter Tyser /*
384ad6884SPeter Tyser * Cirrus Logic EP93xx PLL support.
484ad6884SPeter Tyser *
584ad6884SPeter Tyser * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
684ad6884SPeter Tyser */
784ad6884SPeter Tyser
884ad6884SPeter Tyser #include <common.h>
984ad6884SPeter Tyser #include <asm/arch/ep93xx.h>
1084ad6884SPeter Tyser #include <asm/io.h>
1184ad6884SPeter Tyser #include <div64.h>
1284ad6884SPeter Tyser
1384ad6884SPeter Tyser /*
1484ad6884SPeter Tyser * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
1584ad6884SPeter Tyser *
1684ad6884SPeter Tyser * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
1784ad6884SPeter Tyser * the specified bus in HZ.
1884ad6884SPeter Tyser */
1984ad6884SPeter Tyser
2084ad6884SPeter Tyser /*
2184ad6884SPeter Tyser * return the PLL output frequency
2284ad6884SPeter Tyser *
2384ad6884SPeter Tyser * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
2484ad6884SPeter Tyser * / (X2IPD + 1) / 2^PS
2584ad6884SPeter Tyser */
get_PLLCLK(uint32_t * pllreg)2684ad6884SPeter Tyser static ulong get_PLLCLK(uint32_t *pllreg)
2784ad6884SPeter Tyser {
2884ad6884SPeter Tyser uint8_t i;
2984ad6884SPeter Tyser const uint32_t clkset = readl(pllreg);
3084ad6884SPeter Tyser uint64_t rate = CONFIG_SYS_CLK_FREQ;
3184ad6884SPeter Tyser rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
3284ad6884SPeter Tyser rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
3384ad6884SPeter Tyser do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
3484ad6884SPeter Tyser for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
3584ad6884SPeter Tyser rate >>= 1;
3684ad6884SPeter Tyser
3784ad6884SPeter Tyser return (ulong)rate;
3884ad6884SPeter Tyser }
3984ad6884SPeter Tyser
4084ad6884SPeter Tyser /* return FCLK frequency */
get_FCLK(void)411c16d2e2SSimon Glass ulong get_FCLK(void)
4284ad6884SPeter Tyser {
4384ad6884SPeter Tyser const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
4484ad6884SPeter Tyser struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
4584ad6884SPeter Tyser
4684ad6884SPeter Tyser const uint32_t clkset1 = readl(&syscon->clkset1);
4784ad6884SPeter Tyser const uint8_t fclk_div =
4884ad6884SPeter Tyser fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
4984ad6884SPeter Tyser const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
5084ad6884SPeter Tyser
5184ad6884SPeter Tyser return fclk_rate;
5284ad6884SPeter Tyser }
5384ad6884SPeter Tyser
5484ad6884SPeter Tyser /* return HCLK frequency */
get_HCLK(void)5584ad6884SPeter Tyser ulong get_HCLK(void)
5684ad6884SPeter Tyser {
5784ad6884SPeter Tyser const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
5884ad6884SPeter Tyser struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
5984ad6884SPeter Tyser
6084ad6884SPeter Tyser const uint32_t clkset1 = readl(&syscon->clkset1);
6184ad6884SPeter Tyser const uint8_t hclk_div =
6284ad6884SPeter Tyser hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
6384ad6884SPeter Tyser const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
6484ad6884SPeter Tyser
6584ad6884SPeter Tyser return hclk_rate;
6684ad6884SPeter Tyser }
6784ad6884SPeter Tyser
6884ad6884SPeter Tyser /* return PCLK frequency */
get_PCLK(void)6984ad6884SPeter Tyser ulong get_PCLK(void)
7084ad6884SPeter Tyser {
7184ad6884SPeter Tyser const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
7284ad6884SPeter Tyser struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
7384ad6884SPeter Tyser
7484ad6884SPeter Tyser const uint32_t clkset1 = readl(&syscon->clkset1);
7584ad6884SPeter Tyser const uint8_t pclk_div =
7684ad6884SPeter Tyser pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
7784ad6884SPeter Tyser const ulong pclk_rate = get_HCLK() / pclk_div;
7884ad6884SPeter Tyser
7984ad6884SPeter Tyser return pclk_rate;
8084ad6884SPeter Tyser }
8184ad6884SPeter Tyser
8284ad6884SPeter Tyser /* return UCLK frequency */
get_UCLK(void)8384ad6884SPeter Tyser ulong get_UCLK(void)
8484ad6884SPeter Tyser {
8584ad6884SPeter Tyser struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
8684ad6884SPeter Tyser ulong uclk_rate;
8784ad6884SPeter Tyser
8884ad6884SPeter Tyser const uint32_t value = readl(&syscon->pwrcnt);
8984ad6884SPeter Tyser if (value & SYSCON_PWRCNT_UART_BAUD)
9084ad6884SPeter Tyser uclk_rate = CONFIG_SYS_CLK_FREQ;
9184ad6884SPeter Tyser else
9284ad6884SPeter Tyser uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
9384ad6884SPeter Tyser
9484ad6884SPeter Tyser return uclk_rate;
9584ad6884SPeter Tyser }
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