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Searched refs:TIM2 (Results 1 – 12 of 12) sorted by relevance

/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32-rcc.txt74 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
94 resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
H A Dst,stm32h7-rcc.txt151 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32-rcc.txt117 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
137 resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
H A Dst,stm32h7-rcc.txt70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
/openbmc/u-boot/include/dt-bindings/clock/
H A Dstm32mp1-clks.h19 #define TIM2 6 macro
/openbmc/linux/include/dt-bindings/clock/
H A Dstm32mp1-clks.h19 #define TIM2 6 macro
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32f.c426 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8): in stm32_clk_get_rate()
429 case STM32F7_APB1_CLOCK(TIM2): in stm32_clk_get_rate()
/openbmc/u-boot/arch/arm/dts/
H A Dstm32f429.dtsi81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32f746.dtsi83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
H A Dstm32f429.dtsi101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
/openbmc/qemu/hw/misc/
H A Dstm32l4x5_rcc.c701 APB1ENR1_SET_ENABLE(TIM2); in rcc_update_apb1enr()
/openbmc/linux/drivers/clk/
H A Dclk-stm32mp1.c1883 PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),