Searched refs:REGB_RD32 (Results 1 – 3 of 3) sorted by relevance
171 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0); in ivpu_pll_cmd_send()176 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1); in ivpu_pll_cmd_send()181 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2); in ivpu_pll_cmd_send()186 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_CMD); in ivpu_pll_cmd_send()216 fmin_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMIN_FUSE); in ivpu_pll_init_frequency_ratios()220 fmax_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMAX_FUSE); in ivpu_pll_init_frequency_ratios()665 val = REGB_RD32(VPU_40XX_BUTTRESS_D0I3_CONTROL); in ivpu_boot_d0i3_drive()702 fuse = REGB_RD32(VPU_40XX_BUTTRESS_TILE_FUSE); in ivpu_hw_40xx_info_init()748 val = REGB_RD32(VPU_40XX_BUTTRESS_IP_RESET); in ivpu_hw_40xx_reset()791 u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS); in ivpu_hw_40xx_profiling_freq_reg_set()[all …]
108 if (REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) == BUTTRESS_ALL_IRQ_MASK) { in ivpu_hw_wa_init()153 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0); in ivpu_pll_cmd_send()158 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1); in ivpu_pll_cmd_send()163 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2); in ivpu_pll_cmd_send()167 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_CMD); in ivpu_pll_cmd_send()202 fmin_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMIN_FUSE); in ivpu_pll_init_frequency_ratios()206 fmax_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMAX_FUSE); in ivpu_pll_init_frequency_ratios()620 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL); in ivpu_boot_d0i3_drive()759 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_STATUS); in ivpu_hw_37xx_is_idle()820 pll_curr_ratio = REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL); in ivpu_hw_37xx_reg_pll_freq_get()[all …]
18 #define REGB_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regb, (reg), #reg, __func__) macro