171 	val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0);  in ivpu_pll_cmd_send()
176 	val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1);  in ivpu_pll_cmd_send()
181 	val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2);  in ivpu_pll_cmd_send()
186 	val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_CMD);  in ivpu_pll_cmd_send()
216 	fmin_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMIN_FUSE);  in ivpu_pll_init_frequency_ratios()
220 	fmax_fuse = REGB_RD32(VPU_40XX_BUTTRESS_FMAX_FUSE);  in ivpu_pll_init_frequency_ratios()
665 	val = REGB_RD32(VPU_40XX_BUTTRESS_D0I3_CONTROL);  in ivpu_boot_d0i3_drive()
702 	fuse = REGB_RD32(VPU_40XX_BUTTRESS_TILE_FUSE);  in ivpu_hw_40xx_info_init()
748 	val = REGB_RD32(VPU_40XX_BUTTRESS_IP_RESET);  in ivpu_hw_40xx_reset()
791 	u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);  in ivpu_hw_40xx_profiling_freq_reg_set()
804 		 REGB_RD32(VPU_40XX_BUTTRESS_HM_ATS) ? "Enable" : "Disable");  in ivpu_hw_40xx_ats_print()
809 	u32 val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);  in ivpu_hw_40xx_clock_relinquish_disable()
888 	val = REGB_RD32(VPU_40XX_BUTTRESS_VPU_STATUS);  in ivpu_hw_40xx_is_idle()
933 	pll_curr_ratio = REGB_RD32(VPU_40XX_BUTTRESS_PLL_FREQ);  in ivpu_hw_40xx_reg_pll_freq_get()
941 	return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET);  in ivpu_hw_40xx_reg_telemetry_offset_get()
946 	return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE);  in ivpu_hw_40xx_reg_telemetry_size_get()
951 	return REGB_RD32(VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE);  in ivpu_hw_40xx_reg_telemetry_enable_get()
1056 	u32 status = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;  in ivpu_hw_40xx_irqb_handler()
1066 			 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1),  in ivpu_hw_40xx_irqb_handler()
1067 			 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2));  in ivpu_hw_40xx_irqb_handler()
1073 		ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));  in ivpu_hw_40xx_irqb_handler()
1079 		ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));  in ivpu_hw_40xx_irqb_handler()
1086 			 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW),  in ivpu_hw_40xx_irqb_handler()
1087 			 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH));  in ivpu_hw_40xx_irqb_handler()
1094 			 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW),  in ivpu_hw_40xx_irqb_handler()
1095 			 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH));  in ivpu_hw_40xx_irqb_handler()
1136 	u32 irqb = REGB_RD32(VPU_40XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;  in ivpu_hw_40xx_diagnose_failure()
1152 			 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG1),  in ivpu_hw_40xx_diagnose_failure()
1153 			 REGB_RD32(VPU_40XX_BUTTRESS_ATS_ERR_LOG2));  in ivpu_hw_40xx_diagnose_failure()
1157 		ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI0_ERR_LOG));  in ivpu_hw_40xx_diagnose_failure()
1160 		ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_40XX_BUTTRESS_CFI1_ERR_LOG));  in ivpu_hw_40xx_diagnose_failure()
1164 			 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW),  in ivpu_hw_40xx_diagnose_failure()
1165 			 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH));  in ivpu_hw_40xx_diagnose_failure()
1169 			 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW),  in ivpu_hw_40xx_diagnose_failure()
1170 			 REGB_RD32(VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH));  in ivpu_hw_40xx_diagnose_failure()