108 	if (REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) == BUTTRESS_ALL_IRQ_MASK) {  in ivpu_hw_wa_init()
153 	val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0);  in ivpu_pll_cmd_send()
158 	val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1);  in ivpu_pll_cmd_send()
163 	val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2);  in ivpu_pll_cmd_send()
167 	val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_CMD);  in ivpu_pll_cmd_send()
202 	fmin_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMIN_FUSE);  in ivpu_pll_init_frequency_ratios()
206 	fmax_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMAX_FUSE);  in ivpu_pll_init_frequency_ratios()
620 	val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL);  in ivpu_boot_d0i3_drive()
759 	val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_STATUS);  in ivpu_hw_37xx_is_idle()
820 	pll_curr_ratio = REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL);  in ivpu_hw_37xx_reg_pll_freq_get()
831 	return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_OFFSET);  in ivpu_hw_37xx_reg_telemetry_offset_get()
836 	return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE);  in ivpu_hw_37xx_reg_telemetry_size_get()
841 	return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_ENABLE);  in ivpu_hw_37xx_reg_telemetry_enable_get()
946 	u32 status = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;  in ivpu_hw_37xx_irqb_handler()
954 			 REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL));  in ivpu_hw_37xx_irqb_handler()
963 		u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG);  in ivpu_hw_37xx_irqb_handler()
1008 	u32 irqb = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK;  in ivpu_hw_37xx_diagnose_failure()
1026 		u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG);  in ivpu_hw_37xx_diagnose_failure()