Searched refs:PLLE_AUX (Results 1 – 6 of 6) sorted by relevance
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
H A D | clock.c | 1143 #define PLLE_AUX 0x48c macro 1166 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable() 1168 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable() 1244 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable() 1249 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable() 1255 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
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/openbmc/linux/drivers/clk/tegra/ |
H A D | clk-tegra30.c | 83 #define PLLE_AUX 0x48c macro 874 clk_base + PLLE_AUX, 2, 1, 0, NULL); in tegra30_pll_init() 1031 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init() 1036 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
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H A D | clk-tegra124.c | 62 #define PLLE_AUX 0x48c macro 479 .aux_reg = PLLE_AUX, 1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init() 1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
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H A D | clk-tegra210.c | 92 #define PLLE_AUX 0x48c macro 504 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_is_enabled() 527 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start() 530 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start() 535 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start() 1973 .aux_reg = PLLE_AUX, 3144 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init() 3150 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
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H A D | clk-tegra114.c | 93 #define PLLE_AUX 0x48c macro 563 .aux_reg = PLLE_AUX,
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/openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
H A D | clock.c | 957 #define PLLE_AUX 0x48c macro 970 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable() 973 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
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