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Searched refs:HHI_SYS_PLL_CNTL (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_meson_axg.c195 {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
196 {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
197 {HHI_SYS_PLL_CNTL, 16, 2}, /* pod */
H A Dclk_meson.c683 {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
684 {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
685 {HHI_SYS_PLL_CNTL, 10, 2}, /* pod */
/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.h51 #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ macro
H A Daxg.h96 #define HHI_SYS_PLL_CNTL 0x300 macro
H A Dgxbb.h90 #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ macro
H A Daxg.c95 .reg_off = HHI_SYS_PLL_CNTL,
100 .reg_off = HHI_SYS_PLL_CNTL,
105 .reg_off = HHI_SYS_PLL_CNTL,
110 .reg_off = HHI_SYS_PLL_CNTL,
115 .reg_off = HHI_SYS_PLL_CNTL,
132 .offset = HHI_SYS_PLL_CNTL,
H A Dgxbb.c378 .reg_off = HHI_SYS_PLL_CNTL,
383 .reg_off = HHI_SYS_PLL_CNTL,
388 .reg_off = HHI_SYS_PLL_CNTL,
393 .reg_off = HHI_SYS_PLL_CNTL,
398 .reg_off = HHI_SYS_PLL_CNTL,
415 .offset = HHI_SYS_PLL_CNTL,
H A Dmeson8b.c261 .reg_off = HHI_SYS_PLL_CNTL,
266 .reg_off = HHI_SYS_PLL_CNTL,
271 .reg_off = HHI_SYS_PLL_CNTL,
276 .reg_off = HHI_SYS_PLL_CNTL,
281 .reg_off = HHI_SYS_PLL_CNTL,
301 .offset = HHI_SYS_PLL_CNTL,
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h95 #define HHI_SYS_PLL_CNTL 0x300 macro
H A Dclock-gx.h90 #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ macro