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Searched refs:GETFIELD (Results 1 – 11 of 11) sorted by relevance

/openbmc/qemu/hw/ssi/
H A Dpnv_spi.c76 uint16_t rdr_match_mask = GETFIELD(SPI_MM_RDR_MATCH_MASK, in does_rdr_match()
78 uint16_t rdr_match_val = GETFIELD(SPI_MM_RDR_MATCH_VAL, in does_rdr_match()
82 GETFIELD(PPC_BITMASK(48, 63), s->regs[SPI_RCV_DATA_REG]))) { in does_rdr_match()
164 ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, s->regs[SPI_CLK_CFG_REG]); in spi_response()
196 if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) { in spi_response()
247 return GETFIELD(SPI_STS_SEQ_INDEX, s->status); in get_seq_index()
285 s->N1_bits = GETFIELD(SPI_CTR_CFG_N1, s->regs[SPI_CTR_CFG_REG]); in calculate_N1()
290 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N1()
294 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N1()
308 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B1, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N1()
[all …]
/openbmc/qemu/hw/pci-host/
H A Dpnv_phb3_msi.c109 server = GETFIELD(IODA2_IVT_SERVER, ive); in phb3_msi_try_send()
110 prio = GETFIELD(IODA2_IVT_PRIORITY, ive); in phb3_msi_try_send()
112 pq = GETFIELD(IODA2_IVT_Q, ive) | (GETFIELD(IODA2_IVT_P, ive) << 1); in phb3_msi_try_send()
116 gen = GETFIELD(IODA2_IVT_GEN, ive); in phb3_msi_try_send()
173 pe = GETFIELD(IODA2_IVT_PE, ive); in pnv_phb3_msi_send()
333 if (GETFIELD(IODA2_IVT_PRIORITY, ive) == 0xff) { in pnv_phb3_msi_pic_print_info()
339 GETFIELD(IODA2_IVT_P, ive) ? 'P' : '-', in pnv_phb3_msi_pic_print_info()
340 GETFIELD(IODA2_IVT_Q, ive) ? 'Q' : '-', in pnv_phb3_msi_pic_print_info()
341 (uint32_t) GETFIELD(IODA2_IVT_SERVER, ive) >> 2, in pnv_phb3_msi_pic_print_info()
342 (uint32_t) GETFIELD(IODA2_IVT_PRIORITY, ive), in pnv_phb3_msi_pic_print_info()
[all …]
H A Dpnv_phb3.c177 base = GETFIELD(IODA2_M64BT_BASE, m64) << 20; in pnv_phb3_check_m64()
181 size = GETFIELD(IODA2_M64BT_MASK, m64) << 20; in pnv_phb3_check_m64()
223 server = GETFIELD(IODA2_LXIVT_SERVER, val); in pnv_phb3_lxivt_write()
224 prio = GETFIELD(IODA2_LXIVT_PRIORITY, val); in pnv_phb3_lxivt_write()
239 unsigned int index = GETFIELD(PHB_IODA_AD_TADR, adreg); in pnv_phb3_ioda_access()
240 unsigned int table = GETFIELD(PHB_IODA_AD_TSEL, adreg); in pnv_phb3_ioda_access()
369 local = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]) << 3; in pnv_phb3_remap_irqs()
372 global = GETFIELD(PBCQ_NEST_LSI_SRC, in pnv_phb3_remap_irqs()
384 comp = GETFIELD(PBCQ_NEST_IRSN_COMP, in pnv_phb3_remap_irqs()
386 mask = GETFIELD(PBCQ_NEST_IRSN_COMP, in pnv_phb3_remap_irqs()
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H A Dpnv_phb4.c193 base = GETFIELD(IODA3_MBT0_BASE_ADDR, mbe0) << 12; in pnv_phb4_check_mbt()
194 size = GETFIELD(IODA3_MBT1_MASK, mbe1) << 12; in pnv_phb4_check_mbt()
249 unsigned int index = GETFIELD(PHB_IODA_AD_TADR, adreg); in pnv_phb4_ioda_access()
250 unsigned int table = GETFIELD(PHB_IODA_AD_TSEL, adreg); in pnv_phb4_ioda_access()
366 uint32_t mmask = GETFIELD(PHB_IODA_AD_MIST_PWV, adreg); in pnv_phb4_ioda_write()
482 lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]); in pnv_phb4_update_xsrc()
753 offset = GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, phb->scom_hv_ind_addr_reg); in pnv_phb4_xscom_read()
805 offset = GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, phb->scom_hv_ind_addr_reg); in pnv_phb4_xscom_write()
1175 lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]); in pnv_phb4_set_irq()
1226 uint64_t tta = GETFIELD(IODA3_TVT_TABLE_ADDR, tve); in pnv_phb4_translate_tve()
[all …]
/openbmc/qemu/hw/ppc/
H A Dpnv_i2c.c29 uint8_t port = GETFIELD(I2C_MODE_PORT_NUM, i2c->regs[I2C_MODE_REG]); in pnv_i2c_get_bus()
43 uint16_t front_end = GETFIELD(I2C_RESIDUAL_FRONT_END, in pnv_i2c_update_irq()
45 uint16_t back_end = GETFIELD(I2C_RESIDUAL_BACK_END, in pnv_i2c_update_irq()
47 uint8_t fifo_count = GETFIELD(I2C_STAT_FIFO_ENTRY_COUNT, in pnv_i2c_update_irq()
61 GETFIELD(I2C_WATERMARK_HIGH, i2c->regs[I2C_WATERMARK_REG])) { in pnv_i2c_update_irq()
73 GETFIELD(I2C_WATERMARK_LOW, i2c->regs[I2C_WATERMARK_REG])) { in pnv_i2c_update_irq()
121 uint16_t front_end = GETFIELD(I2C_RESIDUAL_FRONT_END, residual_end); in pnv_i2c_frontend_update()
168 uint8_t addr = GETFIELD(I2C_CMD_DEV_ADDR, val); in pnv_i2c_handle_cmd()
170 uint32_t len_bytes = GETFIELD(I2C_CMD_LEN_BYTES, val); in pnv_i2c_handle_cmd()
209 uint16_t back_end = GETFIELD(I2C_RESIDUAL_BACK_END, residual_end); in pnv_i2c_backend_update()
[all …]
H A Dpnv_chiptod.c250 uint32_t core_id = GETFIELD(TOD_TX_TTYPE_PIB_SLAVE_ADDR, val) & 0x1f; in chiptod_power9_tx_ttype_target()
/openbmc/qemu/hw/intc/
H A Dpnv_xive.c80 blk = GETFIELD(PC_TCTXT_CHIPID, cfg_val); in pnv_xive_block_id()
107 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); in pnv_xive_vst_addr_direct()
147 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; in pnv_xive_vst_addr_indirect()
179 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { in pnv_xive_vst_addr_indirect()
240 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { in pnv_xive_vst_addr()
334 uint8_t blk = GETFIELD(VC_EQC_CWATCH_BLOCKID, in pnv_xive_end_update()
336 uint32_t idx = GETFIELD(VC_EQC_CWATCH_OFFSET, in pnv_xive_end_update()
351 uint8_t blk = GETFIELD(VC_EQC_CWATCH_BLOCKID, in pnv_xive_end_cache_load()
353 uint32_t idx = GETFIELD(VC_EQC_CWATCH_OFFSET, in pnv_xive_end_cache_load()
382 uint8_t blk = GETFIELD(PC_VPC_CWATCH_BLOCKID, in pnv_xive_nvt_update()
[all …]
H A Dpnv_xive2.c98 blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val); in pnv_xive2_block_id()
147 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); in pnv_xive2_vst_addr_direct()
182 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; in pnv_xive2_vst_addr_indirect()
210 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { in pnv_xive2_vst_addr_indirect()
222 uint8_t shift = GETFIELD(PC_NXC_PROC_CONFIG_NVC_TABLE_COMPRESS, in pnv_xive2_nvc_table_compress_shift()
229 uint8_t shift = GETFIELD(PC_NXC_PROC_CONFIG_NVG_TABLE_COMPRESS, in pnv_xive2_nvg_table_compress_shift()
254 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { in pnv_xive2_vst_addr()
446 blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, xive->vc_regs[spec_reg]); in pnv_xive2_end_update()
447 idx = GETFIELD(VC_ENDC_WATCH_INDEX, xive->vc_regs[spec_reg]); in pnv_xive2_end_update()
468 blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, xive->vc_regs[spec_reg]); in pnv_xive2_end_cache_load()
[all …]
/openbmc/qemu/include/hw/ssi/
H A Dpnv_spi_regs.h22 #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m)) macro
/openbmc/qemu/tests/qtest/
H A Dpnv-host-i2c-test.c23 #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m)) macro
135 buf[byte_num] = GETFIELD(I2C_FIFO, reg64); in pnv_i2c_recv()
/openbmc/qemu/target/ppc/
H A Dcpu.h59 #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m)) macro