76     uint16_t rdr_match_mask = GETFIELD(SPI_MM_RDR_MATCH_MASK,  in does_rdr_match()
78     uint16_t rdr_match_val = GETFIELD(SPI_MM_RDR_MATCH_VAL,  in does_rdr_match()
82             GETFIELD(PPC_BITMASK(48, 63), s->regs[SPI_RCV_DATA_REG]))) {  in does_rdr_match()
164         ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, s->regs[SPI_CLK_CFG_REG]);  in spi_response()
196             if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) {  in spi_response()
247     return GETFIELD(SPI_STS_SEQ_INDEX, s->status);  in get_seq_index()
285         s->N1_bits = GETFIELD(SPI_CTR_CFG_N1, s->regs[SPI_CTR_CFG_REG]);  in calculate_N1()
290         if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N1()
294         if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N1()
308         if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B1, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N1()
313             if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B2,  in calculate_N1()
318             if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B3,  in calculate_N1()
331     uint8_t ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL,  in calculate_N1()
406             if (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1) {  in operation_shiftn1()
439             if ((s->N1_rx != 0) && (GETFIELD(SPI_STS_RDR_FULL,  in operation_shiftn1()
463         (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1)) {  in operation_shiftn1()
476        (GETFIELD(SPI_CTR_CFG_N2_CTRL_B0, s->regs[SPI_CTR_CFG_REG]) == 1)) {  in operation_shiftn1()
530         s->N2_bits = GETFIELD(SPI_CTR_CFG_N2, s->regs[SPI_CTR_CFG_REG]);  in calculate_N2()
535         if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N2()
539         if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N2()
550         if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B1, s->regs[SPI_CTR_CFG_REG]) == 1) {  in calculate_N2()
555             if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B3,  in calculate_N2()
560             if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B2,  in calculate_N2()
574     uint8_t ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL,  in calculate_N2()
633             (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1)) {  in operation_shiftn2()
669             (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1)) {  in operation_shiftn2()
726     if (GETFIELD(SPI_STS_SEQ_FSM, s->status) == SEQ_STATE_IDLE) {  in operation_sequencer()
816             if ((GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_IDLE) ||  in operation_sequencer()
817                 (GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_DONE)) {  in operation_sequencer()
819                               "shifter state = 0x%llx", GETFIELD(  in operation_sequencer()
858                     if (GETFIELD(SPI_STS_TDR_UNDERRUN, s->status)) {  in operation_sequencer()
886                               GETFIELD(SPI_STS_SHIFTER_FSM, s->status));  in operation_sequencer()
927             if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) {  in operation_sequencer()
973                 GETFIELD(SPI_CTR_CFG_CMP1, s->regs[SPI_CTR_CFG_REG])) {  in operation_sequencer()
991             uint8_t condition2 = GETFIELD(SPI_CTR_CFG_CMP2,  in operation_sequencer()
1101         if (GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_WAIT) {  in pnv_spi_xscom_read()
1145         if ((GETFIELD(SPI_CLK_CFG_RST_CTRL, s->regs[SPI_CLK_CFG_REG]) == 0x5)  in pnv_spi_xscom_write()
1146              && (GETFIELD(SPI_CLK_CFG_RST_CTRL, val) == 0xA)) {  in pnv_spi_xscom_write()
1177                                   GETFIELD(SPI_STS_RDR, val));  in pnv_spi_xscom_write()
1179                                   GETFIELD(SPI_STS_TDR, val));  in pnv_spi_xscom_write()