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Searched refs:CPURISCVState (Results 1 – 25 of 41) sorted by relevance

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/openbmc/qemu/target/riscv/
H A Dfpu_helper.c27 target_ulong riscv_cpu_get_fflags(CPURISCVState *env) in riscv_cpu_get_fflags()
41 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) in riscv_cpu_set_fflags()
54 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode()
280 uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) in helper_fsqrt_s()
371 uint64_t helper_fround_s(CPURISCVState *env, uint64_t rs1) in helper_fround_s()
439 uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) in helper_fcvt_s_d()
444 uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) in helper_fcvt_d_s()
450 uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) in helper_fsqrt_d()
613 uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) in helper_fsqrt_h()
660 uint64_t helper_fround_h(CPURISCVState *env, uint64_t rs1) in helper_fround_h()
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H A Dpmp.h66 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
68 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
70 void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
71 target_ulong mseccfg_csr_read(CPURISCVState *env);
73 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
76 bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
80 target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr);
81 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
82 void pmp_update_rule_nums(CPURISCVState *env);
83 uint32_t pmp_get_num_rules(CPURISCVState *env);
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H A Dcpu.h36 typedef struct CPUArchState CPURISCVState; typedef
486 CPURISCVState env;
537 uint64_t riscv_cpu_all_pending(CPURISCVState *env);
538 int riscv_cpu_mirq_pending(CPURISCVState *env);
539 int riscv_cpu_sirq_pending(CPURISCVState *env);
540 int riscv_cpu_vsirq_pending(CPURISCVState *env);
541 bool riscv_cpu_fp_enabled(CPURISCVState *env);
544 bool riscv_cpu_vector_enabled(CPURISCVState *env);
571 void riscv_cpu_interrupt(CPURISCVState *env);
699 static inline int riscv_cpu_xlen(CPURISCVState *env) in riscv_cpu_xlen()
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H A Dcsr.c78 static RISCVException fs(CPURISCVState *env, int csrno) in fs()
93 static RISCVException vs(CPURISCVState *env, int csrno) in vs()
106 static RISCVException ctr(CPURISCVState *env, int csrno) in ctr()
162 static RISCVException ctr32(CPURISCVState *env, int csrno) in ctr32()
171 static RISCVException zcmt(CPURISCVState *env, int csrno) in zcmt()
188 static RISCVException mctr(CPURISCVState *env, int csrno) in mctr()
256 static RISCVException any(CPURISCVState *env, int csrno) in any()
261 static RISCVException any32(CPURISCVState *env, int csrno) in any32()
438 static RISCVException sstc(CPURISCVState *env, int csrno) in sstc()
491 static RISCVException satp(CPURISCVState *env, int csrno) in satp()
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H A Ddebug.h134 bool tdata_available(CPURISCVState *env, int tdata_index);
136 target_ulong tselect_csr_read(CPURISCVState *env);
137 void tselect_csr_write(CPURISCVState *env, target_ulong val);
139 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
140 void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
142 target_ulong tinfo_csr_read(CPURISCVState *env);
148 void riscv_trigger_realize(CPURISCVState *env);
149 void riscv_trigger_reset_hold(CPURISCVState *env);
151 bool riscv_itrigger_enabled(CPURISCVState *env);
152 void riscv_itrigger_update_priv(CPURISCVState *env);
H A Dop_helper.c42 target_ulong helper_csrr(CPURISCVState *env, int csr) in helper_csrr()
97 void helper_csrw_i128(CPURISCVState *env, int csr, in helper_csrw_i128()
201 static void check_zicbom_access(CPURISCVState *env, in check_zicbom_access()
262 target_ulong helper_sret(CPURISCVState *env) in helper_sret()
315 target_ulong helper_mret(CPURISCVState *env) in helper_mret()
356 void helper_wfi(CPURISCVState *env) in helper_wfi()
376 void helper_wrs_nto(CPURISCVState *env) in helper_wrs_nto()
387 void helper_tlb_flush(CPURISCVState *env) in helper_tlb_flush()
402 void helper_tlb_flush_all(CPURISCVState *env) in helper_tlb_flush_all()
408 void helper_hyp_tlb_flush(CPURISCVState *env) in helper_hyp_tlb_flush()
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H A Ddebug.c166 target_ulong tselect_csr_read(CPURISCVState *env) in tselect_csr_read()
573 itrigger_get_count(CPURISCVState *env, int index) in itrigger_get_count()
600 bool riscv_itrigger_enabled(CPURISCVState *env) in riscv_itrigger_enabled()
620 void helper_itrigger_match(CPURISCVState *env) in helper_itrigger_match()
693 void riscv_itrigger_update_priv(CPURISCVState *env) in riscv_itrigger_update_priv()
821 target_ulong tinfo_csr_read(CPURISCVState *env) in tinfo_csr_read()
831 CPURISCVState *env = &cpu->env; in riscv_cpu_debug_excp_handler()
847 CPURISCVState *env = &cpu->env; in riscv_cpu_debug_check_breakpoint()
894 CPURISCVState *env = &cpu->env; in riscv_cpu_debug_check_watchpoint()
950 void riscv_trigger_realize(CPURISCVState *env) in riscv_trigger_realize()
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H A Dpmu.h25 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
27 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
31 int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
35 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
37 void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv,
39 RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
H A Dpmp.c30 static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
32 static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
68 uint32_t pmp_get_num_rules(CPURISCVState *env) in pmp_get_num_rules()
144 void pmp_unlock_entries(CPURISCVState *env) in pmp_unlock_entries()
171 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) in pmp_update_rule_addr()
216 void pmp_update_rule_nums(CPURISCVState *env) in pmp_update_rule_nums()
307 bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, in pmp_hart_has_privs()
466 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, in pmpcfg_csr_write()
575 void mseccfg_csr_write(CPURISCVState *env, target_ulong val) in mseccfg_csr_write()
607 target_ulong mseccfg_csr_read(CPURISCVState *env) in mseccfg_csr_read()
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H A Dgdbstub.c54 CPURISCVState *env = &cpu->env; in riscv_cpu_gdb_read_register()
81 CPURISCVState *env = &cpu->env; in riscv_cpu_gdb_write_register()
114 CPURISCVState *env = &cpu->env; in riscv_gdb_get_fpu()
130 CPURISCVState *env = &cpu->env; in riscv_gdb_set_fpu()
142 CPURISCVState *env = &cpu->env; in riscv_gdb_get_vector()
160 CPURISCVState *env = &cpu->env; in riscv_gdb_set_vector()
176 CPURISCVState *env = &cpu->env; in riscv_gdb_get_csr()
193 CPURISCVState *env = &cpu->env; in riscv_gdb_set_csr()
214 CPURISCVState *env = &cpu->env; in riscv_gdb_get_virtual()
243 CPURISCVState *env = &cpu->env; in riscv_gen_dynamic_csr_feature()
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H A Dpmu.c94 CPURISCVState *env = &cpu->env; in riscv_pmu_counter_enabled()
106 CPURISCVState *env = &cpu->env; in riscv_pmu_incr_ctr_rv32()
147 CPURISCVState *env = &cpu->env; in riscv_pmu_incr_ctr_rv64()
192 static void riscv_pmu_icount_update_priv(CPURISCVState *env, in riscv_pmu_icount_update_priv()
232 static void riscv_pmu_cycle_update_priv(CPURISCVState *env, in riscv_pmu_cycle_update_priv()
268 void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, in riscv_pmu_update_fixed_ctrs()
279 CPURISCVState *env = &cpu->env; in riscv_pmu_incr_ctr()
305 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, in riscv_pmu_ctr_monitor_instructions()
379 int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, in riscv_pmu_update_event_map()
423 static bool pmu_hpmevent_is_of_set(CPURISCVState *env, uint32_t ctr_idx) in pmu_hpmevent_is_of_set()
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H A Dinternals.h87 static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) in nanbox_s()
97 static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) in check_nanbox_s()
113 static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) in nanbox_h()
123 static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) in check_nanbox_h()
H A Dcommon-semi-target.h17 CPURISCVState *env = &cpu->env; in common_semi_arg()
24 CPURISCVState *env = &cpu->env; in common_semi_set_ret()
41 CPURISCVState *env = &cpu->env; in common_semi_stack_bottom()
H A Dm128_helper.c25 target_ulong HELPER(divu_i128)(CPURISCVState *env, in HELPER()
45 target_ulong HELPER(remu_i128)(CPURISCVState *env, in HELPER()
65 target_ulong HELPER(divs_i128)(CPURISCVState *env, in HELPER()
90 target_ulong HELPER(rems_i128)(CPURISCVState *env, in HELPER()
H A Dcpu_helper.c152 void riscv_cpu_update_mask(CPURISCVState *env) in riscv_cpu_update_mask()
397 int riscv_cpu_mirq_pending(CPURISCVState *env) in riscv_cpu_mirq_pending()
501 CPURISCVState *env = &cpu->env; in riscv_cpu_exec_interrupt()
513 bool riscv_cpu_fp_enabled(CPURISCVState *env) in riscv_cpu_fp_enabled()
624 CPURISCVState *env = &cpu->env; in riscv_cpu_claim_interrupts()
633 void riscv_cpu_interrupt(CPURISCVState *env) in riscv_cpu_interrupt()
1220 CPURISCVState *env = &cpu->env; in riscv_cpu_get_phys_page_debug()
1247 CPURISCVState *env = &cpu->env; in riscv_cpu_do_transaction_failed()
1268 CPURISCVState *env = &cpu->env; in riscv_cpu_do_unaligned_access()
1315 CPURISCVState *env = &cpu->env; in riscv_cpu_tlb_fill()
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H A Dtranslate.c249 offsetof(CPURISCVState, bins)); in gen_exception_illegal()
259 tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); in gen_exception_inst_addr_mis()
634 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_fs_dirty()
636 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_fs_dirty()
663 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_vs_dirty()
665 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); in mark_vs_dirty()
1119 CPURISCVState *env = cpu_env(cpu); in opcode_at()
1210 CPURISCVState *env = cpu_env(cs); in riscv_tr_init_disas_context()
1266 CPURISCVState *env = cpu_env(cpu); in riscv_tr_translate_insn()
1338 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); in riscv_translate_init()
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H A Dvector_internals.h113 static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc, in vext_get_total_elems()
151 CPURISCVState *env, uint32_t desc) \
190 CPURISCVState *env, uint32_t desc,
196 void *vs2, CPURISCVState *env, \
217 CPURISCVState *env, uint32_t desc,
223 void *vs2, CPURISCVState *env, \
H A Dtime_helper.c28 CPURISCVState *env = &cpu->env; in riscv_vstimer_cb()
43 void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer, in riscv_timer_write_timecmp()
129 CPURISCVState *env; in riscv_timer_init()
H A Dvector_helper.c153 static void NAME(CPURISCVState *env, abi_ptr addr, \
200 target_ulong stride, CPURISCVState *env, in vext_ldst_stride()
345 CPURISCVState *env, uint32_t desc)
354 CPURISCVState *env, uint32_t desc) in HELPER()
473 CPURISCVState *env, uint32_t desc,
618 CPURISCVState *env, uint32_t desc) \
643 CPURISCVState *env, uint32_t desc) \ in GEN_VEXT_LD_WHOLE()
1955 CPURISCVState *env, in vext_vv_rm_1()
1974 CPURISCVState *env, in vext_vv_rm_2()
2082 CPURISCVState *env, in vext_vx_rm_1()
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H A Dmachine.c37 CPURISCVState *env = &cpu->env; in pmp_post_load()
75 CPURISCVState *env = &cpu->env; in hyper_needed()
131 CPURISCVState *env = &cpu->env; in vector_needed()
156 CPURISCVState *env = &cpu->env; in pointermasking_needed()
208 CPURISCVState *env = &cpu->env; in cpu_kvmtimer_post_load()
239 CPURISCVState *env = &cpu->env; in debug_post_load()
266 CPURISCVState *env = &cpu->env; in riscv_cpu_post_load()
296 CPURISCVState *env = &cpu->env; in envcfg_needed()
H A Dth_csr.c36 static RISCVException smode(CPURISCVState *env, int csrno) in smode()
54 static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno, in read_th_sxstatus()
/openbmc/qemu/linux-user/riscv/
H A Dtarget_cpu.h4 static inline void cpu_clone_regs_child(CPURISCVState *env, target_ulong newsp, in cpu_clone_regs_child()
14 static inline void cpu_clone_regs_parent(CPURISCVState *env, unsigned flags) in cpu_clone_regs_parent()
18 static inline void cpu_set_tls(CPURISCVState *env, target_ulong newtls) in cpu_set_tls()
23 static inline abi_ulong get_sp_from_cpustate(CPURISCVState *state) in get_sp_from_cpustate()
H A Dsignal.c63 CPURISCVState *regs, size_t framesize) in get_sigframe()
80 static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env) in setup_sigcontext()
98 CPURISCVState *env, target_sigset_t *set) in setup_ucontext()
115 target_sigset_t *set, CPURISCVState *env) in setup_rt_frame()
147 static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc) in restore_sigcontext()
165 static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc) in restore_ucontext()
182 long do_rt_sigreturn(CPURISCVState *env) in do_rt_sigreturn()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c73 CPURISCVState *env = &cpu->env; in riscv_cpu_write_misa_bit()
98 CPURISCVState *env = &cpu->env; in riscv_cpu_synchronize_from_tb()
116 CPURISCVState *env = &cpu->env; in riscv_restore_state_to_opc()
236 CPURISCVState *env = &cpu->env; in cpu_cfg_ext_auto_update()
289 CPURISCVState *env = &cpu->env; in riscv_cpu_disable_priv_spec_isa_exts()
416 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_set_extensions()
661 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_profile()
769 CPURISCVState *env = &cpu->env; in cpu_enable_implied_rule()
820 CPURISCVState *env = &cpu->env; in cpu_enable_zc_implied_rules()
872 CPURISCVState *env = &cpu->env; in riscv_tcg_cpu_finalize_features()
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/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c196 CPURISCVState *env = &cpu->env; in kvm_cpu_get_misa_ext_cfg()
209 CPURISCVState *env = &cpu->env; in kvm_cpu_set_misa_ext_cfg()
237 CPURISCVState *env = &cpu->env; in kvm_riscv_update_cpu_misa_ext()
422 CPURISCVState *env = &cpu->env; in kvm_riscv_update_cpu_cfg_isa_ext()
766 CPURISCVState *env = &cpu->env; in kvm_riscv_get_regs_vector()
822 CPURISCVState *env = &cpu->env; in kvm_riscv_put_regs_vector()
930 CPURISCVState *env = &cpu->env; in kvm_riscv_init_machine_ids()
959 CPURISCVState *env = &cpu->env; in kvm_riscv_init_misa_ext_mask()
980 CPURISCVState *env = &cpu->env; in kvm_riscv_read_cbomz_blksize()
998 CPURISCVState *env = &cpu->env; in kvm_riscv_read_multiext_legacy()
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