target/riscv/cpu.h

36 typedef struct CPUArchState CPURISCVState;  typedef
486     CPURISCVState env;
517 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)  in riscv_has_ext()
537 uint64_t riscv_cpu_all_pending(CPURISCVState *env);
538 int riscv_cpu_mirq_pending(CPURISCVState *env);
539 int riscv_cpu_sirq_pending(CPURISCVState *env);
540 int riscv_cpu_vsirq_pending(CPURISCVState *env);
541 bool riscv_cpu_fp_enabled(CPURISCVState *env);
542 target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
543 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
544 bool riscv_cpu_vector_enabled(CPURISCVState *env);
545 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
546 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch);
567 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
569 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
571 void riscv_cpu_interrupt(CPURISCVState *env);
573 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
575 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
583 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
586 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en);
589 G_NORETURN void riscv_raise_exception(CPURISCVState *env,
592 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
593 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
623 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
630 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)  in riscv_cpu_cfg()
636 static inline int cpu_address_mode(CPURISCVState *env)  in cpu_address_mode()
646 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode)  in cpu_get_xl()
674 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)  in cpu_recompute_xl()
687 static inline RISCVMXL cpu_address_xl(CPURISCVState *env)  in cpu_address_xl()
699 static inline int riscv_cpu_xlen(CPURISCVState *env)  in riscv_cpu_xlen()
707 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)  in riscv_cpu_sxl()
748 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
751 void riscv_cpu_update_mask(CPURISCVState *env);
754 RISCVException riscv_csrr(CPURISCVState *env, int csrno,
756 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
759 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
764 static inline void riscv_csr_write(CPURISCVState *env, int csrno,  in riscv_csr_write()
770 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)  in riscv_csr_read()
777 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
779 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
781 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
783 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
788 RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
790 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
794 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
796 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
832 void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext);