1*1b3b7693SRichard Henderson /*
2*1b3b7693SRichard Henderson  * Target-specific parts of semihosting/arm-compat-semi.c.
3*1b3b7693SRichard Henderson  *
4*1b3b7693SRichard Henderson  * Copyright (c) 2005, 2007 CodeSourcery.
5*1b3b7693SRichard Henderson  * Copyright (c) 2019, 2022 Linaro
6*1b3b7693SRichard Henderson  * Copyright © 2020 by Keith Packard <keithp@keithp.com>
7*1b3b7693SRichard Henderson  *
8*1b3b7693SRichard Henderson  * SPDX-License-Identifier: GPL-2.0-or-later
9*1b3b7693SRichard Henderson  */
10*1b3b7693SRichard Henderson 
11*1b3b7693SRichard Henderson #ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H
12*1b3b7693SRichard Henderson #define TARGET_RISCV_COMMON_SEMI_TARGET_H
13*1b3b7693SRichard Henderson 
common_semi_arg(CPUState * cs,int argno)14*1b3b7693SRichard Henderson static inline target_ulong common_semi_arg(CPUState *cs, int argno)
15*1b3b7693SRichard Henderson {
16*1b3b7693SRichard Henderson     RISCVCPU *cpu = RISCV_CPU(cs);
17*1b3b7693SRichard Henderson     CPURISCVState *env = &cpu->env;
18*1b3b7693SRichard Henderson     return env->gpr[xA0 + argno];
19*1b3b7693SRichard Henderson }
20*1b3b7693SRichard Henderson 
common_semi_set_ret(CPUState * cs,target_ulong ret)21*1b3b7693SRichard Henderson static inline void common_semi_set_ret(CPUState *cs, target_ulong ret)
22*1b3b7693SRichard Henderson {
23*1b3b7693SRichard Henderson     RISCVCPU *cpu = RISCV_CPU(cs);
24*1b3b7693SRichard Henderson     CPURISCVState *env = &cpu->env;
25*1b3b7693SRichard Henderson     env->gpr[xA0] = ret;
26*1b3b7693SRichard Henderson }
27*1b3b7693SRichard Henderson 
common_semi_sys_exit_extended(CPUState * cs,int nr)28*1b3b7693SRichard Henderson static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr)
29*1b3b7693SRichard Henderson {
30*1b3b7693SRichard Henderson     return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8);
31*1b3b7693SRichard Henderson }
32*1b3b7693SRichard Henderson 
is_64bit_semihosting(CPUArchState * env)33*1b3b7693SRichard Henderson static inline bool is_64bit_semihosting(CPUArchState *env)
34*1b3b7693SRichard Henderson {
35*1b3b7693SRichard Henderson     return riscv_cpu_mxl(env) != MXL_RV32;
36*1b3b7693SRichard Henderson }
37*1b3b7693SRichard Henderson 
common_semi_stack_bottom(CPUState * cs)38*1b3b7693SRichard Henderson static inline target_ulong common_semi_stack_bottom(CPUState *cs)
39*1b3b7693SRichard Henderson {
40*1b3b7693SRichard Henderson     RISCVCPU *cpu = RISCV_CPU(cs);
41*1b3b7693SRichard Henderson     CPURISCVState *env = &cpu->env;
42*1b3b7693SRichard Henderson     return env->gpr[xSP];
43*1b3b7693SRichard Henderson }
44*1b3b7693SRichard Henderson 
common_semi_has_synccache(CPUArchState * env)45*1b3b7693SRichard Henderson static inline bool common_semi_has_synccache(CPUArchState *env)
46*1b3b7693SRichard Henderson {
47*1b3b7693SRichard Henderson     return true;
48*1b3b7693SRichard Henderson }
49*1b3b7693SRichard Henderson 
50*1b3b7693SRichard Henderson #endif
51