Searched refs:CLK_MUX_READ_ONLY (Results 1 – 15 of 15) sorted by relevance
| /openbmc/linux/drivers/clk/zynqmp/ |
| H A D | clk-mux-zynqmp.c | 111 ccf_flag |= CLK_MUX_READ_ONLY; in zynqmp_clk_map_mux_ccf_flags()
146 if (nodes->type_flag & CLK_MUX_READ_ONLY) in zynqmp_clk_register_mux()
|
| /openbmc/linux/drivers/clk/nxp/ |
| H A D | clk-lpc32xx.c | 1114 .ops = (_flags & CLK_MUX_READ_ONLY ? \
1236 CLK_MUX_READ_ONLY),
1238 CLK_MUX_READ_ONLY),
1240 CLK_MUX_READ_ONLY),
1243 CLK_MUX_READ_ONLY),
1245 CLK_MUX_READ_ONLY),
1327 LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY),
|
| H A D | clk-lpc18xx-cgu.c | 220 LPC1XX_CGU_BASE_CLK(SAFE, base_irc_src_ids, CLK_MUX_READ_ONLY),
|
| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-half-divider.c | 186 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops in rockchip_clk_register_halfdiv()
|
| H A D | clk.c | 67 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops in rockchip_clk_register_branch()
|
| H A D | clk-rk3568.c | 530 RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
533 RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY),
|
| H A D | clk-rk3588.c | 1335 RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY,
|
| /openbmc/linux/drivers/clk/renesas/ |
| H A D | rzg2l-cpg.h | 153 .mux_flags = CLK_MUX_READ_ONLY)
|
| /openbmc/linux/drivers/clk/ |
| H A D | clk-mux.c | 177 if (clk_mux_flags & CLK_MUX_READ_ONLY) in __clk_hw_register_mux()
|
| H A D | clk-stm32mp1.c | 920 element->mux.flags = CLK_MUX_READ_ONLY; in clk_register_pll()
|
| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-s3c64xx.c | 125 MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
|
| H A D | clk-s5pv210.c | 370 CLK_MUX_READ_ONLY, 0),
|
| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk.h | 209 …x_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
|
| /openbmc/linux/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra20.c | 2238 pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL); in tegra20_pinctrl_register_clock_muxes()
2241 pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL); in tegra20_pinctrl_register_clock_muxes()
|
| /openbmc/linux/include/linux/ |
| H A D | clk-provider.h | 982 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ macro
|