Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4 |
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#
3f0cdb94 |
| 25-Jun-2023 |
Ye Li <ye.li@nxp.com> |
clk: imx: pllv4: Fix SPLL2 MULT range
The SPLL2 on iMX8ULP is different with other frac PLLs, it can support VCO from 650Mhz to 1Ghz. According to RM, the MULT is using a range from 27 to 54, not so
clk: imx: pllv4: Fix SPLL2 MULT range
The SPLL2 on iMX8ULP is different with other frac PLLs, it can support VCO from 650Mhz to 1Ghz. According to RM, the MULT is using a range from 27 to 54, not some fixed values. If using current PLL implementation, some clock rate can't be supported.
Fix the issue by adding new type for the SPLL2 and use MULT range to replace MULT table
Fixes: 5f0601c47c33 ("clk: imx: Update the pllv4 to support imx8ulp") Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230625123340.4067536-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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Revision tags: v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28 |
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#
6077af23 |
| 06-May-2023 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: drop imx_unregister_clocks
There is no user using imx_unregister_clocks, so drop it.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://
clk: imx: drop imx_unregister_clocks
There is no user using imx_unregister_clocks, so drop it.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230506090856.3599035-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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Revision tags: v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23 |
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#
335aee51 |
| 31-Mar-2023 |
Jacky Bai <ping.bai@nxp.com> |
clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate
If a divider's parent clock has fractional part, it will hard to round out a more accurate clock rate for this divider,
clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate
If a divider's parent clock has fractional part, it will hard to round out a more accurate clock rate for this divider, add the 'CLK_DIVIDER_ROUND_CLOSEST' flags for such divider to get a more accurate clock rate.
Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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#
56b8d0bf |
| 03-Apr-2023 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: fracn-gppll: support integer pll
The fracn gppll could be configured in FRAC or INTEGER mode during hardware design. The current driver only support FRAC mode, while this patch introduces
clk: imx: fracn-gppll: support integer pll
The fracn gppll could be configured in FRAC or INTEGER mode during hardware design. The current driver only support FRAC mode, while this patch introduces INTEGER support. When the PLL is INTEGER pll, there is no mfn, mfd, the calculation is as below: Fvco_clk = (Fref / DIV[RDIV] ) * DIV[MFI] Fclko_odiv = Fvco_clk / DIV[ODIV]
In this patch, we reuse the FRAC pll logic with some condition check to simplify the driver
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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#
79ef82c5 |
| 03-Apr-2023 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: drop duplicated macro
Drop duplicated macro definition
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@l
clk: imx: drop duplicated macro
Drop duplicated macro definition
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403082728.3199849-1-peng.fan@oss.nxp.com
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Revision tags: v6.1.22 |
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#
784a9b39 |
| 23-Mar-2023 |
Adam Ford <aford173@gmail.com> |
clk: imx: Add imx8m_clk_hw_composite_flags macro
In order to set custom flags to imx8m_clk_hw_composite, split it off into a separate macro which can accept additional flags.
Signed-off-by: Adam Fo
clk: imx: Add imx8m_clk_hw_composite_flags macro
In order to set custom flags to imx8m_clk_hw_composite, split it off into a separate macro which can accept additional flags.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-3-aford173@gmail.com
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Revision tags: v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9 |
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#
77577310 |
| 31-Jan-2023 |
Oleksij Rempel <o.rempel@pengutronix.de> |
clk: imx: add imx_obtain_fixed_of_clock()
Add imx_obtain_fixed_of_clock() to optionally add clock not configured in the devicetree.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-
clk: imx: add imx_obtain_fixed_of_clock()
Add imx_obtain_fixed_of_clock() to optionally add clock not configured in the devicetree.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-15-o.rempel@pengutronix.de
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#
ee394f63 |
| 31-Jan-2023 |
Oleksij Rempel <o.rempel@pengutronix.de> |
clk: imx: add clk-gpr-mux driver
Almost(?) every i.MX variant has clk mux for ethernet (rgmii/rmii) reference clock located in the GPR1 register. So far this clk is configured in different ways: - m
clk: imx: add clk-gpr-mux driver
Almost(?) every i.MX variant has clk mux for ethernet (rgmii/rmii) reference clock located in the GPR1 register. So far this clk is configured in different ways: - mach-imx6q is doing mux configuration based on ptp vs enet_ref clk comparison. - mach-imx7d is setting mux to PAD for all boards - mach-imx6ul is setting mux to internal clock for all boards.
Since we have imx7d and imx6ul board variants which do not work with configurations forced by kernel mach code, we need to implement this clk mux properly as part of the clk framework. Which is done by this patch.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230131084642.709385-2-o.rempel@pengutronix.de
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Revision tags: v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4 |
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#
2d5513bf |
| 04-Jan-2023 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: remove clk_count of imx_register_uart_clocks
The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users.
Signed-off-by: Peng Fan <peng.fan@nxp.
clk: imx: remove clk_count of imx_register_uart_clocks
The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com
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Revision tags: v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79 |
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#
8178e245 |
| 13-Nov-2022 |
Dario Binacchi <dario.binacchi@amarulasolutions.com> |
clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()
The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the f
clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()
The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the function, and will allow it to be used not only for fixed rate clocks but also in wider contexts.
No functional changes intended.
The replacements were made with the following command:
grep -rl 'imx_obtain_fixed_clk_hw' ./ | \ xargs sed -i 's/imx_obtain_fixed_clk_hw/imx_get_clk_hw_by_name/g'
Tested on a BSH SystemMaster (SMM) S2 board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20221113180839.1625832-1-dario.binacchi@amarulasolutions.com
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Revision tags: v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64 |
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#
0836c860 |
| 29-Aug-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: add i.MX93 clk gate
i.MX93 LPCG is different from i.MX8M CCGR. Although imx_clk_hw_gate4_flags is used here, it not strictly match i.MX93. i.MX93 has such design: - LPCG_DIRECT use BIT0 a
clk: imx: add i.MX93 clk gate
i.MX93 LPCG is different from i.MX8M CCGR. Although imx_clk_hw_gate4_flags is used here, it not strictly match i.MX93. i.MX93 has such design: - LPCG_DIRECT use BIT0 as on/off gate when LPCG_AUTHEN CPU_LPM is 0 - LPCG_LPM_CUR use BIT[2:0] as on/off gate when LPCG_AUTHEN CPU_LPM is 1
The current implementation suppose CPU_LPM is 0, and use LPCG_DIRECT BIT[1:0] as on/off gate. Although BIT1 is touched, actually BIT1 is reserved.
And imx_clk_hw_gate4_flags use mask 0x3 to determine whether the clk is enabled or not, but i.MX93 LPCG only use BIT0 to control when CPU_LPM is 0. So clk disabled unused during kernel boot not able to gate off the unused clocks.
To match i.MX93 LPCG, introduce imx93_clk_gate.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220830033137.4149542-6-peng.fan@oss.nxp.com
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#
2b66f02e |
| 29-Aug-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: clk-composite-93: check white_list
The CCM ROOT AUTHEN register WHITE_LIST indicate: Each bit in this field represent for one domain. Bit16~Bit31 represent for DOMAIN0~DOMAIN15 respectivel
clk: imx: clk-composite-93: check white_list
The CCM ROOT AUTHEN register WHITE_LIST indicate: Each bit in this field represent for one domain. Bit16~Bit31 represent for DOMAIN0~DOMAIN15 respectively. Only corresponding bit of the domains is set to 1 can change the registers of this Clock Root.
i.MX93 DID is 3, so if BIT(3 + WHITE_LIST_SHIFT) is 0, the clk should be set to read only. To make the imx93_clk_composite_flags be reusable, add a new parameter named did(domain id);
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20220830033137.4149542-5-peng.fan@oss.nxp.com
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Revision tags: v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26 |
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#
19565ea1 |
| 28-Feb-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: add mcore_booted module paratemter
Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX8M, there is CCM(clock control Module) to generate clock root clock, an
clk: imx: add mcore_booted module paratemter
Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX8M, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and CCGR (clock gating) to gate clocks to peripherals. As below: anatop->ccm->ccgr->peripheral
Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for CCGR and CCM, auxiliary core normally only use CCGR hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux.
Per NXP hardware design, because CCGR already support gate to peripherals, and clk root gate power leakage is negligible. So when in AMP case, we could not register the clk root gate.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220228124112.3974242-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
1b26cb8a |
| 27-Feb-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: support fracn gppll
This PLL module is a Fractional-N synthesizer, supporting 30-bit numerator and denominator. Numerator is a signed number. It has feature to adjust fractional portion of
clk: imx: support fracn gppll
This PLL module is a Fractional-N synthesizer, supporting 30-bit numerator and denominator. Numerator is a signed number. It has feature to adjust fractional portion of feedback divider dynamically. This fracn gppll is used in i.MX93.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220228020908.2810346-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
11994196 |
| 27-Feb-2022 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: add i.MX93 composite clk
i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here is to combine all these into one composite clk and simplify clk tree. i.MX93 CCM is a new I
clk: imx: add i.MX93 composite clk
i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here is to combine all these into one composite clk and simplify clk tree. i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220228020908.2810346-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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Revision tags: v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1 |
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#
289ebc4f |
| 03-Nov-2021 |
Alexander Stein <alexander.stein@ew.tq-group.com> |
clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites
Only imx8m_clk_hw_composite_core needs to set this flag.
Fixes: a60fe746df94 ("clk: imx: Rework all imx_clk_hw_composite wrapper
clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites
Only imx8m_clk_hw_composite_core needs to set this flag.
Fixes: a60fe746df94 ("clk: imx: Rework all imx_clk_hw_composite wrappers") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103123947.3222443-1-alexander.stein@ew.tq-group.com Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65 |
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#
9179d239 |
| 14-Sep-2021 |
Jacky Bai <ping.bai@nxp.com> |
clk: imx: Update the pfdv2 for 8ulp specific support
On i.MX8ULP, the 'CLK_SET_RATE_PARENT' flag should NOT be set and according to the laest RM, the PFD divider value range seems will be changed in
clk: imx: Update the pfdv2 for 8ulp specific support
On i.MX8ULP, the 'CLK_SET_RATE_PARENT' flag should NOT be set and according to the laest RM, the PFD divider value range seems will be changed in the future, so update the pfdv2 to include the specific support for i.MX8ULP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-8-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
b40ba806 |
| 14-Sep-2021 |
Jacky Bai <ping.bai@nxp.com> |
clk: imx: Update the compsite driver to support imx8ulp
On i.MX8ULP, some peripherals have a sw_rst control resides in the per device PCC clock control register, all others are same as i.MX7ULP, so
clk: imx: Update the compsite driver to support imx8ulp
On i.MX8ULP, some peripherals have a sw_rst control resides in the per device PCC clock control register, all others are same as i.MX7ULP, so update the 7ulp clock composite driver to support i.MX8ULP to maxmimize the code reuse.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-4-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
5f0601c4 |
| 14-Sep-2021 |
Jacky Bai <ping.bai@nxp.com> |
clk: imx: Update the pllv4 to support imx8ulp
The PLLs used on i.MX8ULP is mostly the same as on i.MX7ULP, except the PLL register offset is changed. Change the PLLv4 driver for code reuse on i.MX7U
clk: imx: Update the pllv4 to support imx8ulp
The PLLs used on i.MX8ULP is mostly the same as on i.MX7ULP, except the PLL register offset is changed. Change the PLLv4 driver for code reuse on i.MX7ULP and i.MX8ULP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-3-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
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#
6b4a6b7f |
| 13-Sep-2021 |
Abel Vesa <abel.vesa@nxp.com> |
clk: imx: Rework imx_clk_hw_pll14xx wrapper
It looks much cleaner to just have a macro compared to having a function that passes NULL as dev to the lower-level imx_dev_clk_hw_pll14xx.
Signed-off-by
clk: imx: Rework imx_clk_hw_pll14xx wrapper
It looks much cleaner to just have a macro compared to having a function that passes NULL as dev to the lower-level imx_dev_clk_hw_pll14xx.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-9-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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#
a60fe746 |
| 13-Sep-2021 |
Abel Vesa <abel.vesa@nxp.com> |
clk: imx: Rework all imx_clk_hw_composite wrappers
Rather than having multiple different macros for each different type of imx8m_clk_hw_composite, implement them in such a way so we can take advanta
clk: imx: Rework all imx_clk_hw_composite wrappers
Rather than having multiple different macros for each different type of imx8m_clk_hw_composite, implement them in such a way so we can take advantage the most of the already defined simpler types. Basically, we end up having one low-level __imx8m_clk_hw_composite function, a wrapper to simplify the parents related arguments called _imx8m_clk_hw_composite and then all the types can use those for each specific case.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-8-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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b170586a |
| 13-Sep-2021 |
Abel Vesa <abel.vesa@nxp.com> |
clk: imx: Rework all clk_hw_register_divider wrappers
Instead of having multiple inline functions that were calling clk_hw_register_divider, implement a generic low-level __imx_clk_hw_divider and im
clk: imx: Rework all clk_hw_register_divider wrappers
Instead of having multiple inline functions that were calling clk_hw_register_divider, implement a generic low-level __imx_clk_hw_divider and implement the rest as macros that pass on as arguments whatever is needed in each case.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-7-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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004989ab |
| 13-Sep-2021 |
Abel Vesa <abel.vesa@nxp.com> |
clk: imx: Rework all clk_hw_register_mux wrappers
Instead of having multiple inline functions that were calling clk_hw_register_mux, implement a generic low-level __imx_clk_hw_mux and implement the
clk: imx: Rework all clk_hw_register_mux wrappers
Instead of having multiple inline functions that were calling clk_hw_register_mux, implement a generic low-level __imx_clk_hw_mux and implement the rest as macros that pass on as arguments whatever is needed in each case.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-6-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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66173dbe |
| 13-Sep-2021 |
Abel Vesa <abel.vesa@nxp.com> |
clk: imx: Rework all clk_hw_register_gate2 wrappers
Instead of having multiple inline functions that were calling clk_hw_register_gate2, implement a generic low-level __imx_clk_hw_gate2 and implemen
clk: imx: Rework all clk_hw_register_gate2 wrappers
Instead of having multiple inline functions that were calling clk_hw_register_gate2, implement a generic low-level __imx_clk_hw_gate2 and implement the rest as macros that pass on as arguments whatever is needed in each case.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-5-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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f121cca2 |
| 13-Sep-2021 |
Abel Vesa <abel.vesa@nxp.com> |
clk: imx: Rework all clk_hw_register_gate wrappers
Instead of having multiple inline functions that were calling clk_hw_register_gate, implement a generic low-level __imx_clk_hw_gate and implement t
clk: imx: Rework all clk_hw_register_gate wrappers
Instead of having multiple inline functions that were calling clk_hw_register_gate, implement a generic low-level __imx_clk_hw_gate and implement the rest as macros that pass on as arguments whatever is needed in each case.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-4-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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