| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt2701.c | 940 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
942 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
944 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
946 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,
948 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
950 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
952 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
954 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
956 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
958 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
[all …]
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| H A D | clk-mt6797.c | 619 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
627 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000100, PLL_AO,
629 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000010, 0, 7,
631 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000100, 0, 21,
633 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000120, 0, 21,
635 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000120, 0, 21,
637 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000120, 0, 21,
639 PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000120, 0, 21,
641 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000120, 0, 21,
643 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000130, 0, 31,
[all …]
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| H A D | clk-mt6779.c | 1184 PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
1188 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,
1190 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,
1193 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,
1196 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,
1198 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,
1200 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,
1202 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,
1205 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,
1208 PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,
[all …]
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| H A D | clk-mt6765.c | 695 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
705 PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, 0,
707 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, 0,
709 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, 0,
711 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, 0,
714 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, 0,
716 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, 0,
718 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, 0,
720 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, 0,
722 PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, 0,
[all …]
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| H A D | clk-mt7629.c | 44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
313 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
315 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
317 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
319 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
321 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
323 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | fsl,plldig.yaml | 14 interface in the display core, as implemented in TSMC CLN28HPM PLL.
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
32 of this PLL cannot be changed during runtime only at startup. Therefore,
35 its own desired VCO frequency for the PLL.
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| H A D | axs10x-i2s-pll-clock.txt | 1 Binding for the AXS10X I2S PLL clock
9 - reg : address and length of the I2S PLL register set.
10 - clocks: shall be the input parent clock phandle for the PLL.
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| H A D | vt8500.txt | 9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
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| H A D | snps,pll-clock.txt | 1 Binding for the AXS10X Generic PLL clock
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
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| H A D | allwinner,sun6i-a31-pll6-clk.yaml | 7 title: Allwinner A31 Peripheral PLL
19 The first output is the regular PLL output, the second is a PLL
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| H A D | allwinner,sun4i-a10-pll6-clk.yaml | 7 title: Allwinner A10 Peripheral PLL
20 regular PLL output, the third is a PLL output at twice the rate.
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| H A D | qcom,dispcc-sc8280xp.yaml | 38 - description: DSI 0 PLL byte clock
39 - description: DSI 0 PLL DSI clock
40 - description: DSI 1 PLL byte clock
41 - description: DSI 1 PLL DSI clock
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| H A D | qoriq-clock.txt | 5 multiple phase locked loops (PLL) to create a variety of frequencies
70 platform PLL.
117 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
118 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
125 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
126 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
132 * 0 - equal to the PLL frequency
133 * 1 - equal to the PLL frequency divided by 2
134 * 2 - equal to the PLL frequency divided by 4
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| H A D | baikal,bt1-ccu-div.yaml | 96 - description: CCU SATA PLL output clock
97 - description: CCU PCIe PLL output clock
98 - description: CCU Ethernet PLL output clock
111 - description: CCU SATA PLL output clock
112 - description: CCU PCIe PLL output clock
113 - description: CCU Ethernet PLL output clock
182 # Required Clock Control Unit PLL node:
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| /openbmc/u-boot/doc/device-tree-bindings/phy/ |
| H A D | phy-stm32-usbphyc.txt | 6 PLL configuration.
9 |_ PLL
25 - clocks: phandle + clock specifier for the PLL phy clock
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
31 - assigned-clock-parents: the PLL phy clock parent
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| /openbmc/linux/Documentation/devicetree/bindings/cpufreq/ |
| H A D | nvidia,tegra124-cpufreq.txt | 12 - pll_x: Fast PLL clocksource.
13 - pll_p: Auxiliary PLL used during fast PLL rate changes.
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-exynos5410.c | 243 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
245 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
247 [epll] = PLL(pll_2650x, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
249 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
251 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
253 [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
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| /openbmc/linux/Documentation/admin-guide/media/ |
| H A D | technisat.rst | 58 #) => ``Generic I2C PLL based tuners``
63 #) => ``Generic I2C PLL based tuners``
80 #) => ``Generic I2C PLL based tuners``
85 #) => ``Generic I2C PLL based tuners``
94 #) => ``Generic I2C PLL based tuners``
|
| /openbmc/u-boot/arch/arm/mach-davinci/ |
| H A D | Kconfig | 67 comment "DA850 PLL Initialization Parameters"
76 int "PLLC0 PLL Post-Divider"
79 Value written to PLLC0 PLL Post-Divider Control Register
124 hex "PLLC1 PLL Post-Divider"
127 Value written to PLLC1 PLL Post-Divider Control Register
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 44 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
50 PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
52 PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
54 PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
56 PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
58 PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
60 PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
62 PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0,
64 PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0,
66 PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0,
[all …]
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-iio-frequency-adf4350 | 7 the fractional-N PLL. It is assumed that the algorithm
16 applications, the reference frequency used by the PLL may
21 down the PLL and its RFOut buffers during REFin changes.
|
| /openbmc/linux/drivers/iio/frequency/ |
| H A D | Kconfig | 6 # Phase-Locked Loop (PLL) frequency synthesizers
10 menu "Frequency Synthesizers DDS/PLL"
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
88 Downconverter with integrated Fractional-N PLL and VCO.
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| /openbmc/linux/drivers/clk/mstar/ |
| H A D | Kconfig | 7 Support for the CPU PLL present on MStar/Sigmastar SoCs.
15 Support for the MPLL PLL and dividers block present on
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| /openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | adv7343.txt | 14 micro ampere level. All DACs and the internal PLL
16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
17 internal PLL 1 circuit to be powered down and the
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | brcm,cygnus-audio.txt | 12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
15 (usually the PLL)
|