16d7489c7SEugeniy PaltsevBinding for the AXS10X Generic PLL clock 26d7489c7SEugeniy Paltsev 36d7489c7SEugeniy PaltsevThis binding uses the common clock binding[1]. 46d7489c7SEugeniy Paltsev 56d7489c7SEugeniy Paltsev[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 66d7489c7SEugeniy Paltsev 76d7489c7SEugeniy PaltsevRequired properties: 86d7489c7SEugeniy Paltsev- compatible: should be "snps,axs10x-<name>-pll-clock" 96d7489c7SEugeniy Paltsev "snps,axs10x-arc-pll-clock" 106d7489c7SEugeniy Paltsev "snps,axs10x-pgu-pll-clock" 116d7489c7SEugeniy Paltsev- reg: should always contain 2 pairs address - length: first for PLL config 126d7489c7SEugeniy Paltsevregisters and second for corresponding LOCK CGU register. 136d7489c7SEugeniy Paltsev- clocks: shall be the input parent clock phandle for the PLL. 146d7489c7SEugeniy Paltsev- #clock-cells: from common clock binding; Should always be set to 0. 156d7489c7SEugeniy Paltsev 166d7489c7SEugeniy PaltsevExample: 176d7489c7SEugeniy Paltsev input-clk: input-clk { 186d7489c7SEugeniy Paltsev clock-frequency = <33333333>; 196d7489c7SEugeniy Paltsev compatible = "fixed-clock"; 206d7489c7SEugeniy Paltsev #clock-cells = <0>; 216d7489c7SEugeniy Paltsev }; 226d7489c7SEugeniy Paltsev 236d7489c7SEugeniy Paltsev core-clk: core-clk@80 { 246d7489c7SEugeniy Paltsev compatible = "snps,axs10x-arc-pll-clock"; 256d7489c7SEugeniy Paltsev reg = <0x80 0x10>, <0x100 0x10>; 266d7489c7SEugeniy Paltsev #clock-cells = <0>; 276d7489c7SEugeniy Paltsev clocks = <&input-clk>; 286d7489c7SEugeniy Paltsev }; 29