Searched hist:"8 d2c749e" (Results 1 – 3 of 3) sorted by relevance
/openbmc/linux/include/soc/mediatek/ |
H A D | smi.h | 8d2c749e Mon Jan 11 05:19:11 CST 2021 Yong Wu <yong.wu@mediatek.com> iommu/mediatek: Support master use iova over 32bit
After extending v7s, our pagetable already support iova reach 16GB(34bit). the master got the iova via dma_alloc_attrs may reach 34bits, but its HW register still is 32bit. then how to set the bit32/bit33 iova? this depend on a SMI larb setting(bank_sel).
we separate whole 16GB iova to four banks: bank: 0: 0~4G; 1: 4~8G; 2: 8-12G; 3: 12-16G; The bank number is (iova >> 32).
We will preassign which bank the larbs belong to. currently we don't have a interface for master to adjust its bank number.
Each a bank is a iova_region which is a independent iommu-domain. the iova range for each iommu-domain can't cross 4G.
Signed-off-by: Yong Wu <yong.wu@mediatek.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> #for memory part Reviewed-by: Tomasz Figa <tfiga@chromium.org> Link: https://lore.kernel.org/r/20210111111914.22211-31-yong.wu@mediatek.com Signed-off-by: Will Deacon <will@kernel.org>
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/openbmc/linux/drivers/memory/ |
H A D | mtk-smi.c | 8d2c749e Mon Jan 11 05:19:11 CST 2021 Yong Wu <yong.wu@mediatek.com> iommu/mediatek: Support master use iova over 32bit
After extending v7s, our pagetable already support iova reach 16GB(34bit). the master got the iova via dma_alloc_attrs may reach 34bits, but its HW register still is 32bit. then how to set the bit32/bit33 iova? this depend on a SMI larb setting(bank_sel).
we separate whole 16GB iova to four banks: bank: 0: 0~4G; 1: 4~8G; 2: 8-12G; 3: 12-16G; The bank number is (iova >> 32).
We will preassign which bank the larbs belong to. currently we don't have a interface for master to adjust its bank number.
Each a bank is a iova_region which is a independent iommu-domain. the iova range for each iommu-domain can't cross 4G.
Signed-off-by: Yong Wu <yong.wu@mediatek.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> #for memory part Reviewed-by: Tomasz Figa <tfiga@chromium.org> Link: https://lore.kernel.org/r/20210111111914.22211-31-yong.wu@mediatek.com Signed-off-by: Will Deacon <will@kernel.org>
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/openbmc/linux/drivers/iommu/ |
H A D | mtk_iommu.c | 8d2c749e Mon Jan 11 05:19:11 CST 2021 Yong Wu <yong.wu@mediatek.com> iommu/mediatek: Support master use iova over 32bit
After extending v7s, our pagetable already support iova reach 16GB(34bit). the master got the iova via dma_alloc_attrs may reach 34bits, but its HW register still is 32bit. then how to set the bit32/bit33 iova? this depend on a SMI larb setting(bank_sel).
we separate whole 16GB iova to four banks: bank: 0: 0~4G; 1: 4~8G; 2: 8-12G; 3: 12-16G; The bank number is (iova >> 32).
We will preassign which bank the larbs belong to. currently we don't have a interface for master to adjust its bank number.
Each a bank is a iova_region which is a independent iommu-domain. the iova range for each iommu-domain can't cross 4G.
Signed-off-by: Yong Wu <yong.wu@mediatek.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> #for memory part Reviewed-by: Tomasz Figa <tfiga@chromium.org> Link: https://lore.kernel.org/r/20210111111914.22211-31-yong.wu@mediatek.com Signed-off-by: Will Deacon <will@kernel.org>
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