11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2cc8bbe1aSYong Wu /*
3cc8bbe1aSYong Wu * Copyright (c) 2015-2016 MediaTek Inc.
4cc8bbe1aSYong Wu * Author: Yong Wu <yong.wu@mediatek.com>
5cc8bbe1aSYong Wu */
64e508b25SChengci.Xu #include <linux/arm-smccc.h>
7cc8bbe1aSYong Wu #include <linux/clk.h>
8cc8bbe1aSYong Wu #include <linux/component.h>
9cc8bbe1aSYong Wu #include <linux/device.h>
10cc8bbe1aSYong Wu #include <linux/err.h>
11cc8bbe1aSYong Wu #include <linux/io.h>
128956500eSYong Wu #include <linux/iopoll.h>
134f608d38SYong Wu #include <linux/module.h>
14cc8bbe1aSYong Wu #include <linux/of.h>
15cc8bbe1aSYong Wu #include <linux/of_platform.h>
16cc8bbe1aSYong Wu #include <linux/platform_device.h>
17cc8bbe1aSYong Wu #include <linux/pm_runtime.h>
184e508b25SChengci.Xu #include <linux/soc/mediatek/mtk_sip_svc.h>
19cc8bbe1aSYong Wu #include <soc/mediatek/smi.h>
203c8f4ad8SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h>
2166a28915SYong Wu #include <dt-bindings/memory/mtk-memory-port.h>
22cc8bbe1aSYong Wu
23534e0ad2SYong Wu /* SMI COMMON */
24431e9cabSYong Wu #define SMI_L1LEN 0x100
25431e9cabSYong Wu
260d97f217SAngeloGioacchino Del Regno #define SMI_L1_ARB 0x200
27534e0ad2SYong Wu #define SMI_BUS_SEL 0x220
28534e0ad2SYong Wu #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
29534e0ad2SYong Wu /* All are MMU0 defaultly. Only specialize mmu1 here. */
30534e0ad2SYong Wu #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
31e6dec923SYong Wu
320d97f217SAngeloGioacchino Del Regno #define SMI_READ_FIFO_TH 0x230
33431e9cabSYong Wu #define SMI_M4U_TH 0x234
34431e9cabSYong Wu #define SMI_FIFO_TH1 0x238
35431e9cabSYong Wu #define SMI_FIFO_TH2 0x23c
36431e9cabSYong Wu #define SMI_DCM 0x300
37431e9cabSYong Wu #define SMI_DUMMY 0x444
38431e9cabSYong Wu
39534e0ad2SYong Wu /* SMI LARB */
408956500eSYong Wu #define SMI_LARB_SLP_CON 0xc
418956500eSYong Wu #define SLP_PROT_EN BIT(0)
428956500eSYong Wu #define SLP_PROT_RDY BIT(16)
438956500eSYong Wu
44fe6dd2a4SYong Wu #define SMI_LARB_CMD_THRT_CON 0x24
45fe6dd2a4SYong Wu #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4)
46fe6dd2a4SYong Wu #define SMI_LARB_THRT_RD_NU_LMT (5 << 4)
47fe6dd2a4SYong Wu
48fe6dd2a4SYong Wu #define SMI_LARB_SW_FLAG 0x40
49fe6dd2a4SYong Wu #define SMI_LARB_SW_FLAG_1 0x1
50fe6dd2a4SYong Wu
51fe6dd2a4SYong Wu #define SMI_LARB_OSTDL_PORT 0x200
52fe6dd2a4SYong Wu #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2))
53a8529f3bSFabien Parent
54534e0ad2SYong Wu /* Below are about mmu enable registers, they are different in SoCs */
55534e0ad2SYong Wu /* gen1: mt2701 */
563c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_BASE 0x5c0
573c8f4ad8SHonghui Zhang
583c8f4ad8SHonghui Zhang /* every register control 8 port, register offset 0x4 */
593c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
603c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_ADDR(id) \
613c8f4ad8SHonghui Zhang (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
623c8f4ad8SHonghui Zhang
633c8f4ad8SHonghui Zhang /*
643c8f4ad8SHonghui Zhang * every port have 4 bit to control, bit[port + 3] control virtual or physical,
653c8f4ad8SHonghui Zhang * bit[port + 2 : port + 1] control the domain, bit[port] control the security
663c8f4ad8SHonghui Zhang * or non-security.
673c8f4ad8SHonghui Zhang */
683c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
693c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
703c8f4ad8SHonghui Zhang /* mt2701 domain should be set to 3 */
713c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
723c8f4ad8SHonghui Zhang
73534e0ad2SYong Wu /* gen2: */
74534e0ad2SYong Wu /* mt8167 */
75534e0ad2SYong Wu #define MT8167_SMI_LARB_MMU_EN 0xfc0
76534e0ad2SYong Wu
77534e0ad2SYong Wu /* mt8173 */
78534e0ad2SYong Wu #define MT8173_SMI_LARB_MMU_EN 0xf00
79534e0ad2SYong Wu
80534e0ad2SYong Wu /* general */
81e6dec923SYong Wu #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
82e6dec923SYong Wu #define F_MMU_EN BIT(0)
838d2c749eSYong Wu #define BANK_SEL(id) ({ \
848d2c749eSYong Wu u32 _id = (id) & 0x3; \
858d2c749eSYong Wu (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
868d2c749eSYong Wu })
87e6dec923SYong Wu
88431e9cabSYong Wu #define SMI_COMMON_INIT_REGS_NR 6
89fe6dd2a4SYong Wu #define SMI_LARB_PORT_NR_MAX 32
90fe6dd2a4SYong Wu
91fe6dd2a4SYong Wu #define MTK_SMI_FLAG_THRT_UPDATE BIT(0)
92fe6dd2a4SYong Wu #define MTK_SMI_FLAG_SW_FLAG BIT(1)
938956500eSYong Wu #define MTK_SMI_FLAG_SLEEP_CTL BIT(2)
944e508b25SChengci.Xu #define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3)
95fe6dd2a4SYong Wu #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x)))
96431e9cabSYong Wu
97431e9cabSYong Wu struct mtk_smi_reg_pair {
98431e9cabSYong Wu unsigned int offset;
99431e9cabSYong Wu u32 value;
100431e9cabSYong Wu };
101431e9cabSYong Wu
102a5c18986SYong Wu enum mtk_smi_type {
10342d42c76SYong Wu MTK_SMI_GEN1,
10447404757SYong Wu MTK_SMI_GEN2, /* gen2 smi common */
10547404757SYong Wu MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */
10642d42c76SYong Wu };
10742d42c76SYong Wu
1080e14917cSYong Wu /* larbs: Require apb/smi clocks while gals is optional. */
1090e14917cSYong Wu static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"};
1100e14917cSYong Wu #define MTK_SMI_LARB_REQ_CLK_NR 2
1110e14917cSYong Wu #define MTK_SMI_LARB_OPT_CLK_NR 1
1120e14917cSYong Wu
1130e14917cSYong Wu /*
1140e14917cSYong Wu * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required.
1153e4f74e0SYong Wu * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required.
1160e14917cSYong Wu */
1170e14917cSYong Wu static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"};
118205e1776SAngeloGioacchino Del Regno #define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks)
1190e14917cSYong Wu #define MTK_SMI_COM_REQ_CLK_NR 2
1200e14917cSYong Wu #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX
1213e4f74e0SYong Wu #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3
1220e14917cSYong Wu
12342d42c76SYong Wu struct mtk_smi_common_plat {
124a5c18986SYong Wu enum mtk_smi_type type;
12564fea74aSYong Wu bool has_gals;
126567e58cfSYong Wu u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
127431e9cabSYong Wu
128431e9cabSYong Wu const struct mtk_smi_reg_pair *init;
12942d42c76SYong Wu };
13042d42c76SYong Wu
1313c8f4ad8SHonghui Zhang struct mtk_smi_larb_gen {
1323c8f4ad8SHonghui Zhang int port_in_larb[MTK_LARB_NR_MAX + 1];
1338c1561edSChengci.Xu int (*config_port)(struct device *dev);
1342e9b0908SYong Wu unsigned int larb_direct_to_common_mask;
135fe6dd2a4SYong Wu unsigned int flags_general;
136fe6dd2a4SYong Wu const u8 (*ostd)[SMI_LARB_PORT_NR_MAX];
1373c8f4ad8SHonghui Zhang };
138cc8bbe1aSYong Wu
139cc8bbe1aSYong Wu struct mtk_smi {
140cc8bbe1aSYong Wu struct device *dev;
1410e14917cSYong Wu unsigned int clk_num;
1420e14917cSYong Wu struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX];
1433c8f4ad8SHonghui Zhang struct clk *clk_async; /*only needed by mt2701*/
144567e58cfSYong Wu union {
145567e58cfSYong Wu void __iomem *smi_ao_base; /* only for gen1 */
146567e58cfSYong Wu void __iomem *base; /* only for gen2 */
147567e58cfSYong Wu };
14847404757SYong Wu struct device *smi_common_dev; /* for sub common */
14942d42c76SYong Wu const struct mtk_smi_common_plat *plat;
150cc8bbe1aSYong Wu };
151cc8bbe1aSYong Wu
152cc8bbe1aSYong Wu struct mtk_smi_larb { /* larb: local arbiter */
153cc8bbe1aSYong Wu struct mtk_smi smi;
154cc8bbe1aSYong Wu void __iomem *base;
15547404757SYong Wu struct device *smi_common_dev; /* common or sub-common dev */
1563c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen;
1573c8f4ad8SHonghui Zhang int larbid;
158cc8bbe1aSYong Wu u32 *mmu;
1598d2c749eSYong Wu unsigned char *bank;
160cc8bbe1aSYong Wu };
161cc8bbe1aSYong Wu
162cc8bbe1aSYong Wu static int
mtk_smi_larb_bind(struct device * dev,struct device * master,void * data)163cc8bbe1aSYong Wu mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
164cc8bbe1aSYong Wu {
165cc8bbe1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev);
1661ee9feb2SYong Wu struct mtk_smi_larb_iommu *larb_mmu = data;
167cc8bbe1aSYong Wu unsigned int i;
168cc8bbe1aSYong Wu
169ec2da07cSYong Wu for (i = 0; i < MTK_LARB_NR_MAX; i++) {
1701ee9feb2SYong Wu if (dev == larb_mmu[i].dev) {
171ec2da07cSYong Wu larb->larbid = i;
1721ee9feb2SYong Wu larb->mmu = &larb_mmu[i].mmu;
1738d2c749eSYong Wu larb->bank = larb_mmu[i].bank;
174cc8bbe1aSYong Wu return 0;
175cc8bbe1aSYong Wu }
176cc8bbe1aSYong Wu }
177cc8bbe1aSYong Wu return -ENODEV;
178cc8bbe1aSYong Wu }
179cc8bbe1aSYong Wu
180534e0ad2SYong Wu static void
mtk_smi_larb_unbind(struct device * dev,struct device * master,void * data)181534e0ad2SYong Wu mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
182e6dec923SYong Wu {
183534e0ad2SYong Wu /* Do nothing as the iommu is always enabled. */
184e6dec923SYong Wu }
185e6dec923SYong Wu
186534e0ad2SYong Wu static const struct component_ops mtk_smi_larb_component_ops = {
187534e0ad2SYong Wu .bind = mtk_smi_larb_bind,
188534e0ad2SYong Wu .unbind = mtk_smi_larb_unbind,
189534e0ad2SYong Wu };
190a8529f3bSFabien Parent
mtk_smi_larb_config_port_gen1(struct device * dev)1918c1561edSChengci.Xu static int mtk_smi_larb_config_port_gen1(struct device *dev)
1923c8f4ad8SHonghui Zhang {
1933c8f4ad8SHonghui Zhang struct mtk_smi_larb *larb = dev_get_drvdata(dev);
1943c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
1953c8f4ad8SHonghui Zhang struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
1963c8f4ad8SHonghui Zhang int i, m4u_port_id, larb_port_num;
1973c8f4ad8SHonghui Zhang u32 sec_con_val, reg_val;
1983c8f4ad8SHonghui Zhang
1993c8f4ad8SHonghui Zhang m4u_port_id = larb_gen->port_in_larb[larb->larbid];
2003c8f4ad8SHonghui Zhang larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
2013c8f4ad8SHonghui Zhang - larb_gen->port_in_larb[larb->larbid];
2023c8f4ad8SHonghui Zhang
2033c8f4ad8SHonghui Zhang for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
2043c8f4ad8SHonghui Zhang if (*larb->mmu & BIT(i)) {
2053c8f4ad8SHonghui Zhang /* bit[port + 3] controls the virtual or physical */
2063c8f4ad8SHonghui Zhang sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
2073c8f4ad8SHonghui Zhang } else {
2083c8f4ad8SHonghui Zhang /* do not need to enable m4u for this port */
2093c8f4ad8SHonghui Zhang continue;
2103c8f4ad8SHonghui Zhang }
2113c8f4ad8SHonghui Zhang reg_val = readl(common->smi_ao_base
2123c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
2133c8f4ad8SHonghui Zhang reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
2143c8f4ad8SHonghui Zhang reg_val |= sec_con_val;
2153c8f4ad8SHonghui Zhang reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
2163c8f4ad8SHonghui Zhang writel(reg_val,
2173c8f4ad8SHonghui Zhang common->smi_ao_base
2183c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
2193c8f4ad8SHonghui Zhang }
2208c1561edSChengci.Xu return 0;
2213c8f4ad8SHonghui Zhang }
2223c8f4ad8SHonghui Zhang
mtk_smi_larb_config_port_mt8167(struct device * dev)2238c1561edSChengci.Xu static int mtk_smi_larb_config_port_mt8167(struct device *dev)
224cc8bbe1aSYong Wu {
225534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev);
226534e0ad2SYong Wu
227534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
2288c1561edSChengci.Xu return 0;
229cc8bbe1aSYong Wu }
230cc8bbe1aSYong Wu
mtk_smi_larb_config_port_mt8173(struct device * dev)2318c1561edSChengci.Xu static int mtk_smi_larb_config_port_mt8173(struct device *dev)
232534e0ad2SYong Wu {
233534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev);
234cc8bbe1aSYong Wu
235534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
2368c1561edSChengci.Xu return 0;
237534e0ad2SYong Wu }
2383c8f4ad8SHonghui Zhang
mtk_smi_larb_config_port_gen2_general(struct device * dev)2398c1561edSChengci.Xu static int mtk_smi_larb_config_port_gen2_general(struct device *dev)
240534e0ad2SYong Wu {
241534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev);
242fe6dd2a4SYong Wu u32 reg, flags_general = larb->larb_gen->flags_general;
243383a44aeSYong Wu const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL;
2444e508b25SChengci.Xu struct arm_smccc_res res;
245534e0ad2SYong Wu int i;
246534e0ad2SYong Wu
247534e0ad2SYong Wu if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
2488c1561edSChengci.Xu return 0;
249534e0ad2SYong Wu
250fe6dd2a4SYong Wu if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) {
251fe6dd2a4SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);
252fe6dd2a4SYong Wu reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK;
253fe6dd2a4SYong Wu reg |= SMI_LARB_THRT_RD_NU_LMT;
254fe6dd2a4SYong Wu writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);
255fe6dd2a4SYong Wu }
256fe6dd2a4SYong Wu
257fe6dd2a4SYong Wu if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG))
258fe6dd2a4SYong Wu writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);
259fe6dd2a4SYong Wu
260fe6dd2a4SYong Wu for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)
261fe6dd2a4SYong Wu writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
262fe6dd2a4SYong Wu
2634e508b25SChengci.Xu /*
2644e508b25SChengci.Xu * When mmu_en bits are in security world, the bank_sel still is in the
2654e508b25SChengci.Xu * LARB_NONSEC_CON below. And the mmu_en bits of LARB_NONSEC_CON have no
2664e508b25SChengci.Xu * effect in this case.
2674e508b25SChengci.Xu */
2684e508b25SChengci.Xu if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) {
2694e508b25SChengci.Xu arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, IOMMU_ATF_CMD_CONFIG_SMI_LARB,
2704e508b25SChengci.Xu larb->larbid, *larb->mmu, 0, 0, 0, 0, &res);
2714e508b25SChengci.Xu if (res.a0 != 0) {
2724e508b25SChengci.Xu dev_err(dev, "Enable iommu fail, ret %ld\n", res.a0);
2734e508b25SChengci.Xu return -EINVAL;
2744e508b25SChengci.Xu }
2754e508b25SChengci.Xu }
2764e508b25SChengci.Xu
277534e0ad2SYong Wu for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
278534e0ad2SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
279534e0ad2SYong Wu reg |= F_MMU_EN;
280534e0ad2SYong Wu reg |= BANK_SEL(larb->bank[i]);
281534e0ad2SYong Wu writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
282534e0ad2SYong Wu }
2838c1561edSChengci.Xu return 0;
284534e0ad2SYong Wu }
285a8529f3bSFabien Parent
286673e71dfSChengci.Xu static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
287673e71dfSChengci.Xu [0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
288673e71dfSChengci.Xu [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
289673e71dfSChengci.Xu [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},
290673e71dfSChengci.Xu [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
291673e71dfSChengci.Xu [4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,},
292673e71dfSChengci.Xu [5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,},
293673e71dfSChengci.Xu [6] = {0x06, 0x01, 0x06, 0x0a,},
294673e71dfSChengci.Xu [7] = {0x0c, 0x0c, 0x12,},
295673e71dfSChengci.Xu [8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14,
296673e71dfSChengci.Xu 0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05,
297673e71dfSChengci.Xu 0x03, 0x01, 0x1e, 0x01, 0x05,},
298673e71dfSChengci.Xu [9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10,
299673e71dfSChengci.Xu 0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,},
300673e71dfSChengci.Xu [10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
301673e71dfSChengci.Xu 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
302673e71dfSChengci.Xu 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
303673e71dfSChengci.Xu [11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
304673e71dfSChengci.Xu 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
305673e71dfSChengci.Xu 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
306673e71dfSChengci.Xu [12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
307673e71dfSChengci.Xu 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
308673e71dfSChengci.Xu 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
309673e71dfSChengci.Xu [13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
310673e71dfSChengci.Xu 0x07, 0x02, 0x04, 0x02, 0x05, 0x05,},
311673e71dfSChengci.Xu [14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02,
312673e71dfSChengci.Xu 0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
313673e71dfSChengci.Xu 0x02, 0x02, 0x01, 0x01,},
314673e71dfSChengci.Xu [15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c,
315673e71dfSChengci.Xu 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02,
316673e71dfSChengci.Xu 0x0c, 0x01, 0x01,},
317673e71dfSChengci.Xu [16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d,
318673e71dfSChengci.Xu 0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,},
319673e71dfSChengci.Xu [17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
320673e71dfSChengci.Xu 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
321673e71dfSChengci.Xu [18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
322673e71dfSChengci.Xu 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
323673e71dfSChengci.Xu [19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
324673e71dfSChengci.Xu [20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
325673e71dfSChengci.Xu [21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
326673e71dfSChengci.Xu 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
327673e71dfSChengci.Xu 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
328673e71dfSChengci.Xu [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,
329673e71dfSChengci.Xu 0x01,},
330673e71dfSChengci.Xu [23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,},
331673e71dfSChengci.Xu [24] = {0x12, 0x06, 0x12, 0x06,},
332673e71dfSChengci.Xu [25] = {0x01},
333673e71dfSChengci.Xu };
334673e71dfSChengci.Xu
335fe6dd2a4SYong Wu static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
336fe6dd2a4SYong Wu [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */
337fe6dd2a4SYong Wu [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */
338fe6dd2a4SYong Wu [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */
339fe6dd2a4SYong Wu [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
340fe6dd2a4SYong Wu [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,},
341fe6dd2a4SYong Wu [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,},
342fe6dd2a4SYong Wu [6] = {0x06, 0x01, 0x06, 0x0a,},
343fe6dd2a4SYong Wu [7] = {0x0c, 0x0c, 0x12,},
344fe6dd2a4SYong Wu [8] = {0x0c, 0x0c, 0x12,},
345fe6dd2a4SYong Wu [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a,
346fe6dd2a4SYong Wu 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,},
347fe6dd2a4SYong Wu [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10,
348fe6dd2a4SYong Wu 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d,
349fe6dd2a4SYong Wu 0x0d, 0x06, 0x10, 0x10,},
350fe6dd2a4SYong Wu [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,},
351fe6dd2a4SYong Wu [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,},
352fe6dd2a4SYong Wu [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,},
353fe6dd2a4SYong Wu [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01,
354fe6dd2a4SYong Wu 0x01, 0x02, 0x02, 0x08, 0x02,},
355fe6dd2a4SYong Wu [15] = {},
356fe6dd2a4SYong Wu [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
357fe6dd2a4SYong Wu 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,},
358fe6dd2a4SYong Wu [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
359fe6dd2a4SYong Wu [18] = {0x12, 0x06, 0x12, 0x06,},
360fe6dd2a4SYong Wu [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
361fe6dd2a4SYong Wu 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
362fe6dd2a4SYong Wu 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
363fe6dd2a4SYong Wu [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
364fe6dd2a4SYong Wu 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
365fe6dd2a4SYong Wu 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
366fe6dd2a4SYong Wu [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
367fe6dd2a4SYong Wu [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
368fe6dd2a4SYong Wu [23] = {0x18, 0x01,},
369fe6dd2a4SYong Wu [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01,
370fe6dd2a4SYong Wu 0x01, 0x01,},
371fe6dd2a4SYong Wu [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
372fe6dd2a4SYong Wu 0x02, 0x01,},
373fe6dd2a4SYong Wu [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
374fe6dd2a4SYong Wu 0x02, 0x01,},
375fe6dd2a4SYong Wu [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
376fe6dd2a4SYong Wu 0x02, 0x01,},
377fe6dd2a4SYong Wu [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
378fe6dd2a4SYong Wu };
379fe6dd2a4SYong Wu
3803c8f4ad8SHonghui Zhang static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
3813c8f4ad8SHonghui Zhang .port_in_larb = {
3823c8f4ad8SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
3833c8f4ad8SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
3843c8f4ad8SHonghui Zhang },
3853c8f4ad8SHonghui Zhang .config_port = mtk_smi_larb_config_port_gen1,
3863c8f4ad8SHonghui Zhang };
3873c8f4ad8SHonghui Zhang
388e6dec923SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
3892e9b0908SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general,
3902e9b0908SYong Wu .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
391e6dec923SYong Wu };
392e6dec923SYong Wu
393fc492f33SMing-Fan Chen static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
394fc492f33SMing-Fan Chen .config_port = mtk_smi_larb_config_port_gen2_general,
395fc492f33SMing-Fan Chen .larb_direct_to_common_mask =
396fc492f33SMing-Fan Chen BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
397fc492f33SMing-Fan Chen /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
398fc492f33SMing-Fan Chen };
399fc492f33SMing-Fan Chen
400534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
401534e0ad2SYong Wu /* mt8167 do not need the port in larb */
402534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8167,
403534e0ad2SYong Wu };
404534e0ad2SYong Wu
405534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
406534e0ad2SYong Wu /* mt8173 do not need the port in larb */
407534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8173,
408534e0ad2SYong Wu };
409534e0ad2SYong Wu
410907ba6a1SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
411907ba6a1SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general,
412907ba6a1SYong Wu .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
413907ba6a1SYong Wu /* IPU0 | IPU1 | CCU */
414907ba6a1SYong Wu };
415907ba6a1SYong Wu
41686a010bfSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
41786a010bfSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general,
41886a010bfSYong Wu .flags_general = MTK_SMI_FLAG_SLEEP_CTL,
41986a010bfSYong Wu };
42086a010bfSYong Wu
421673e71dfSChengci.Xu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
422673e71dfSChengci.Xu .config_port = mtk_smi_larb_config_port_gen2_general,
423673e71dfSChengci.Xu .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
424673e71dfSChengci.Xu MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL,
425673e71dfSChengci.Xu .ostd = mtk_smi_larb_mt8188_ostd,
426673e71dfSChengci.Xu };
427673e71dfSChengci.Xu
42802c02ddcSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
42902c02ddcSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general,
43002c02ddcSYong Wu };
43102c02ddcSYong Wu
432cc4f9dcdSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = {
433cc4f9dcdSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general,
43412fbfd66SAngeloGioacchino Del Regno .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
43512fbfd66SAngeloGioacchino Del Regno MTK_SMI_FLAG_SLEEP_CTL,
436fe6dd2a4SYong Wu .ostd = mtk_smi_larb_mt8195_ostd,
437cc4f9dcdSYong Wu };
438cc4f9dcdSYong Wu
4393c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_larb_of_ids[] = {
440534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
441534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
442534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
4430d97f217SAngeloGioacchino Del Regno {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173},
444534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
445534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
446534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
44786a010bfSYong Wu {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
448673e71dfSChengci.Xu {.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188},
449534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
450cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
4513c8f4ad8SHonghui Zhang {}
4523c8f4ad8SHonghui Zhang };
4533c8f4ad8SHonghui Zhang
mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb * larb)4548956500eSYong Wu static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb)
4558956500eSYong Wu {
4568956500eSYong Wu int ret;
4578956500eSYong Wu u32 tmp;
4588956500eSYong Wu
4598956500eSYong Wu writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON);
4608956500eSYong Wu ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON,
4618956500eSYong Wu tmp, !!(tmp & SLP_PROT_RDY), 10, 1000);
4628956500eSYong Wu if (ret) {
4638956500eSYong Wu /* TODO: Reset this larb if it fails here. */
4648956500eSYong Wu dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp);
4658956500eSYong Wu }
4668956500eSYong Wu return ret;
4678956500eSYong Wu }
4688956500eSYong Wu
mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb * larb)4698956500eSYong Wu static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb)
4708956500eSYong Wu {
4718956500eSYong Wu writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);
4728956500eSYong Wu }
4738956500eSYong Wu
mtk_smi_device_link_common(struct device * dev,struct device ** com_dev)47447404757SYong Wu static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev)
47547404757SYong Wu {
47647404757SYong Wu struct platform_device *smi_com_pdev;
47747404757SYong Wu struct device_node *smi_com_node;
47847404757SYong Wu struct device *smi_com_dev;
47947404757SYong Wu struct device_link *link;
48047404757SYong Wu
48147404757SYong Wu smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
48247404757SYong Wu if (!smi_com_node)
48347404757SYong Wu return -EINVAL;
48447404757SYong Wu
48547404757SYong Wu smi_com_pdev = of_find_device_by_node(smi_com_node);
48647404757SYong Wu of_node_put(smi_com_node);
48747404757SYong Wu if (smi_com_pdev) {
48847404757SYong Wu /* smi common is the supplier, Make sure it is ready before */
489038ae37cSMiaoqian Lin if (!platform_get_drvdata(smi_com_pdev)) {
490038ae37cSMiaoqian Lin put_device(&smi_com_pdev->dev);
49147404757SYong Wu return -EPROBE_DEFER;
492038ae37cSMiaoqian Lin }
49347404757SYong Wu smi_com_dev = &smi_com_pdev->dev;
49447404757SYong Wu link = device_link_add(dev, smi_com_dev,
49547404757SYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
49647404757SYong Wu if (!link) {
49747404757SYong Wu dev_err(dev, "Unable to link smi-common dev\n");
498038ae37cSMiaoqian Lin put_device(&smi_com_pdev->dev);
49947404757SYong Wu return -ENODEV;
50047404757SYong Wu }
50147404757SYong Wu *com_dev = smi_com_dev;
50247404757SYong Wu } else {
50347404757SYong Wu dev_err(dev, "Failed to get the smi_common device\n");
50447404757SYong Wu return -EINVAL;
50547404757SYong Wu }
50647404757SYong Wu return 0;
50747404757SYong Wu }
50847404757SYong Wu
mtk_smi_dts_clk_init(struct device * dev,struct mtk_smi * smi,const char * const clks[],unsigned int clk_nr_required,unsigned int clk_nr_optional)5090e14917cSYong Wu static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
5100e14917cSYong Wu const char * const clks[],
5110e14917cSYong Wu unsigned int clk_nr_required,
5120e14917cSYong Wu unsigned int clk_nr_optional)
5130e14917cSYong Wu {
5140e14917cSYong Wu int i, ret;
5150e14917cSYong Wu
5160e14917cSYong Wu for (i = 0; i < clk_nr_required; i++)
5170e14917cSYong Wu smi->clks[i].id = clks[i];
5180e14917cSYong Wu ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
5190e14917cSYong Wu if (ret)
5200e14917cSYong Wu return ret;
5210e14917cSYong Wu
5220e14917cSYong Wu for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++)
5230e14917cSYong Wu smi->clks[i].id = clks[i];
5240e14917cSYong Wu ret = devm_clk_bulk_get_optional(dev, clk_nr_optional,
5250e14917cSYong Wu smi->clks + clk_nr_required);
5260e14917cSYong Wu smi->clk_num = clk_nr_required + clk_nr_optional;
5270e14917cSYong Wu return ret;
5280e14917cSYong Wu }
5290e14917cSYong Wu
mtk_smi_larb_probe(struct platform_device * pdev)530cc8bbe1aSYong Wu static int mtk_smi_larb_probe(struct platform_device *pdev)
531cc8bbe1aSYong Wu {
532cc8bbe1aSYong Wu struct mtk_smi_larb *larb;
533cc8bbe1aSYong Wu struct device *dev = &pdev->dev;
5340e14917cSYong Wu int ret;
535cc8bbe1aSYong Wu
536cc8bbe1aSYong Wu larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
537cc8bbe1aSYong Wu if (!larb)
538cc8bbe1aSYong Wu return -ENOMEM;
539cc8bbe1aSYong Wu
54075487860SHonghui Zhang larb->larb_gen = of_device_get_match_data(dev);
541912fea8bSYong Wu larb->base = devm_platform_ioremap_resource(pdev, 0);
542cc8bbe1aSYong Wu if (IS_ERR(larb->base))
543cc8bbe1aSYong Wu return PTR_ERR(larb->base);
544cc8bbe1aSYong Wu
5450e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks,
5460e14917cSYong Wu MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR);
5470e14917cSYong Wu if (ret)
5480e14917cSYong Wu return ret;
549cc8bbe1aSYong Wu
550cc8bbe1aSYong Wu larb->smi.dev = dev;
551cc8bbe1aSYong Wu
55247404757SYong Wu ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev);
55347404757SYong Wu if (ret < 0)
55447404757SYong Wu return ret;
555cc8bbe1aSYong Wu
556cc8bbe1aSYong Wu pm_runtime_enable(dev);
557cc8bbe1aSYong Wu platform_set_drvdata(pdev, larb);
55830b869e7SYong Wu ret = component_add(dev, &mtk_smi_larb_component_ops);
55930b869e7SYong Wu if (ret)
56030b869e7SYong Wu goto err_pm_disable;
56130b869e7SYong Wu return 0;
56230b869e7SYong Wu
56330b869e7SYong Wu err_pm_disable:
56430b869e7SYong Wu pm_runtime_disable(dev);
56530b869e7SYong Wu device_link_remove(dev, larb->smi_common_dev);
56630b869e7SYong Wu return ret;
567cc8bbe1aSYong Wu }
568cc8bbe1aSYong Wu
mtk_smi_larb_remove(struct platform_device * pdev)569cc8bbe1aSYong Wu static int mtk_smi_larb_remove(struct platform_device *pdev)
570cc8bbe1aSYong Wu {
5716ce2c05bSYong Wu struct mtk_smi_larb *larb = platform_get_drvdata(pdev);
5726ce2c05bSYong Wu
5736ce2c05bSYong Wu device_link_remove(&pdev->dev, larb->smi_common_dev);
574cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev);
575cc8bbe1aSYong Wu component_del(&pdev->dev, &mtk_smi_larb_component_ops);
576cc8bbe1aSYong Wu return 0;
577cc8bbe1aSYong Wu }
578cc8bbe1aSYong Wu
mtk_smi_larb_resume(struct device * dev)5794f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
5804f0a1a1aSYong Wu {
5814f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev);
5824f0a1a1aSYong Wu const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
5834f0a1a1aSYong Wu int ret;
5844f0a1a1aSYong Wu
5850e14917cSYong Wu ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks);
586a6945f45SYong Wu if (ret)
5874f0a1a1aSYong Wu return ret;
5884f0a1a1aSYong Wu
5898956500eSYong Wu if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL))
5908956500eSYong Wu mtk_smi_larb_sleep_ctrl_disable(larb);
5918956500eSYong Wu
5924f0a1a1aSYong Wu /* Configure the basic setting for this larb */
5938c1561edSChengci.Xu return larb_gen->config_port(dev);
5944f0a1a1aSYong Wu }
5954f0a1a1aSYong Wu
mtk_smi_larb_suspend(struct device * dev)5964f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
5974f0a1a1aSYong Wu {
5984f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev);
5998956500eSYong Wu int ret;
6008956500eSYong Wu
6018956500eSYong Wu if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) {
6028956500eSYong Wu ret = mtk_smi_larb_sleep_ctrl_enable(larb);
6038956500eSYong Wu if (ret)
6048956500eSYong Wu return ret;
6058956500eSYong Wu }
6064f0a1a1aSYong Wu
6070e14917cSYong Wu clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks);
6084f0a1a1aSYong Wu return 0;
6094f0a1a1aSYong Wu }
6104f0a1a1aSYong Wu
6114f0a1a1aSYong Wu static const struct dev_pm_ops smi_larb_pm_ops = {
6124f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
613fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
614fb03082aSYong Wu pm_runtime_force_resume)
6154f0a1a1aSYong Wu };
6164f0a1a1aSYong Wu
617cc8bbe1aSYong Wu static struct platform_driver mtk_smi_larb_driver = {
618cc8bbe1aSYong Wu .probe = mtk_smi_larb_probe,
619cc8bbe1aSYong Wu .remove = mtk_smi_larb_remove,
620cc8bbe1aSYong Wu .driver = {
621cc8bbe1aSYong Wu .name = "mtk-smi-larb",
622cc8bbe1aSYong Wu .of_match_table = mtk_smi_larb_of_ids,
6234f0a1a1aSYong Wu .pm = &smi_larb_pm_ops,
624cc8bbe1aSYong Wu }
625cc8bbe1aSYong Wu };
626cc8bbe1aSYong Wu
6270d97f217SAngeloGioacchino Del Regno static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = {
6280d97f217SAngeloGioacchino Del Regno {SMI_L1_ARB, 0x1b},
6290d97f217SAngeloGioacchino Del Regno {SMI_M4U_TH, 0xce810c85},
6300d97f217SAngeloGioacchino Del Regno {SMI_FIFO_TH1, 0x43214c8},
6310d97f217SAngeloGioacchino Del Regno {SMI_READ_FIFO_TH, 0x191f},
6320d97f217SAngeloGioacchino Del Regno };
6330d97f217SAngeloGioacchino Del Regno
634431e9cabSYong Wu static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
635431e9cabSYong Wu {SMI_L1LEN, 0xb},
636431e9cabSYong Wu {SMI_M4U_TH, 0xe100e10},
637431e9cabSYong Wu {SMI_FIFO_TH1, 0x506090a},
638431e9cabSYong Wu {SMI_FIFO_TH2, 0x506090a},
639431e9cabSYong Wu {SMI_DCM, 0x4f1},
640431e9cabSYong Wu {SMI_DUMMY, 0x1},
641431e9cabSYong Wu };
642431e9cabSYong Wu
64342d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
644a5c18986SYong Wu .type = MTK_SMI_GEN1,
64542d42c76SYong Wu };
64642d42c76SYong Wu
64742d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
648a5c18986SYong Wu .type = MTK_SMI_GEN2,
64942d42c76SYong Wu };
65042d42c76SYong Wu
651fc492f33SMing-Fan Chen static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
652a5c18986SYong Wu .type = MTK_SMI_GEN2,
653fc492f33SMing-Fan Chen .has_gals = true,
654fc492f33SMing-Fan Chen .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
655fc492f33SMing-Fan Chen F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
656fc492f33SMing-Fan Chen };
657fc492f33SMing-Fan Chen
6580d97f217SAngeloGioacchino Del Regno static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = {
6590d97f217SAngeloGioacchino Del Regno .type = MTK_SMI_GEN2,
6600d97f217SAngeloGioacchino Del Regno .bus_sel = F_MMU1_LARB(0),
6610d97f217SAngeloGioacchino Del Regno .init = mtk_smi_common_mt6795_init,
6620d97f217SAngeloGioacchino Del Regno };
6630d97f217SAngeloGioacchino Del Regno
664907ba6a1SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
665a5c18986SYong Wu .type = MTK_SMI_GEN2,
666907ba6a1SYong Wu .has_gals = true,
667567e58cfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
668567e58cfSYong Wu F_MMU1_LARB(7),
669907ba6a1SYong Wu };
670907ba6a1SYong Wu
67186a010bfSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = {
67286a010bfSYong Wu .type = MTK_SMI_GEN2,
67386a010bfSYong Wu .has_gals = true,
67486a010bfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7),
67586a010bfSYong Wu };
67686a010bfSYong Wu
677673e71dfSChengci.Xu static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vdo = {
678673e71dfSChengci.Xu .type = MTK_SMI_GEN2,
679673e71dfSChengci.Xu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(5) | F_MMU1_LARB(7),
680673e71dfSChengci.Xu .init = mtk_smi_common_mt8195_init,
681673e71dfSChengci.Xu };
682673e71dfSChengci.Xu
683673e71dfSChengci.Xu static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = {
684673e71dfSChengci.Xu .type = MTK_SMI_GEN2,
685673e71dfSChengci.Xu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
686673e71dfSChengci.Xu .init = mtk_smi_common_mt8195_init,
687673e71dfSChengci.Xu };
688673e71dfSChengci.Xu
68902c02ddcSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
690a5c18986SYong Wu .type = MTK_SMI_GEN2,
69102c02ddcSYong Wu .has_gals = true,
69202c02ddcSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
69302c02ddcSYong Wu F_MMU1_LARB(6),
69402c02ddcSYong Wu };
69502c02ddcSYong Wu
696cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
697cc4f9dcdSYong Wu .type = MTK_SMI_GEN2,
698cc4f9dcdSYong Wu .has_gals = true,
699cc4f9dcdSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
700cc4f9dcdSYong Wu F_MMU1_LARB(7),
701431e9cabSYong Wu .init = mtk_smi_common_mt8195_init,
702cc4f9dcdSYong Wu };
703cc4f9dcdSYong Wu
704cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
705cc4f9dcdSYong Wu .type = MTK_SMI_GEN2,
706cc4f9dcdSYong Wu .has_gals = true,
707cc4f9dcdSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
708431e9cabSYong Wu .init = mtk_smi_common_mt8195_init,
709cc4f9dcdSYong Wu };
710cc4f9dcdSYong Wu
711cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
712cc4f9dcdSYong Wu .type = MTK_SMI_GEN2_SUB_COMM,
713cc4f9dcdSYong Wu .has_gals = true,
714cc4f9dcdSYong Wu };
715cc4f9dcdSYong Wu
716*3ec0e1eaSAlexandre Mergnat static const struct mtk_smi_common_plat mtk_smi_common_mt8365 = {
717*3ec0e1eaSAlexandre Mergnat .type = MTK_SMI_GEN2,
718*3ec0e1eaSAlexandre Mergnat .bus_sel = F_MMU1_LARB(2) | F_MMU1_LARB(4),
719*3ec0e1eaSAlexandre Mergnat };
720*3ec0e1eaSAlexandre Mergnat
7213c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_common_of_ids[] = {
722534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
723534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
724534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
7250d97f217SAngeloGioacchino Del Regno {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795},
726534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
727534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
728534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
72986a010bfSYong Wu {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
730673e71dfSChengci.Xu {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo},
731673e71dfSChengci.Xu {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp},
732534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
733cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
734cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
735cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},
736*3ec0e1eaSAlexandre Mergnat {.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365},
7373c8f4ad8SHonghui Zhang {}
7383c8f4ad8SHonghui Zhang };
7393c8f4ad8SHonghui Zhang
mtk_smi_common_probe(struct platform_device * pdev)740cc8bbe1aSYong Wu static int mtk_smi_common_probe(struct platform_device *pdev)
741cc8bbe1aSYong Wu {
742cc8bbe1aSYong Wu struct device *dev = &pdev->dev;
743cc8bbe1aSYong Wu struct mtk_smi *common;
7440e14917cSYong Wu int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR;
745cc8bbe1aSYong Wu
746cc8bbe1aSYong Wu common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
747cc8bbe1aSYong Wu if (!common)
748cc8bbe1aSYong Wu return -ENOMEM;
749cc8bbe1aSYong Wu common->dev = dev;
75042d42c76SYong Wu common->plat = of_device_get_match_data(dev);
751cc8bbe1aSYong Wu
7523e4f74e0SYong Wu if (common->plat->has_gals) {
7533e4f74e0SYong Wu if (common->plat->type == MTK_SMI_GEN2)
7540e14917cSYong Wu clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
7553e4f74e0SYong Wu else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
7563e4f74e0SYong Wu clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR;
7573e4f74e0SYong Wu }
7580e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0);
7590e14917cSYong Wu if (ret)
7600e14917cSYong Wu return ret;
76164fea74aSYong Wu
7623c8f4ad8SHonghui Zhang /*
7633c8f4ad8SHonghui Zhang * for mtk smi gen 1, we need to get the ao(always on) base to config
7643c8f4ad8SHonghui Zhang * m4u port, and we need to enable the aync clock for transform the smi
7653c8f4ad8SHonghui Zhang * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
7663c8f4ad8SHonghui Zhang * base.
7673c8f4ad8SHonghui Zhang */
768a5c18986SYong Wu if (common->plat->type == MTK_SMI_GEN1) {
769912fea8bSYong Wu common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0);
7703c8f4ad8SHonghui Zhang if (IS_ERR(common->smi_ao_base))
7713c8f4ad8SHonghui Zhang return PTR_ERR(common->smi_ao_base);
7723c8f4ad8SHonghui Zhang
7733c8f4ad8SHonghui Zhang common->clk_async = devm_clk_get(dev, "async");
7743c8f4ad8SHonghui Zhang if (IS_ERR(common->clk_async))
7753c8f4ad8SHonghui Zhang return PTR_ERR(common->clk_async);
7763c8f4ad8SHonghui Zhang
77746cc815dSArvind Yadav ret = clk_prepare_enable(common->clk_async);
77846cc815dSArvind Yadav if (ret)
77946cc815dSArvind Yadav return ret;
780567e58cfSYong Wu } else {
781912fea8bSYong Wu common->base = devm_platform_ioremap_resource(pdev, 0);
782567e58cfSYong Wu if (IS_ERR(common->base))
783567e58cfSYong Wu return PTR_ERR(common->base);
7843c8f4ad8SHonghui Zhang }
78547404757SYong Wu
78647404757SYong Wu /* link its smi-common if this is smi-sub-common */
78747404757SYong Wu if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
78847404757SYong Wu ret = mtk_smi_device_link_common(dev, &common->smi_common_dev);
78947404757SYong Wu if (ret < 0)
79047404757SYong Wu return ret;
79147404757SYong Wu }
79247404757SYong Wu
793cc8bbe1aSYong Wu pm_runtime_enable(dev);
794cc8bbe1aSYong Wu platform_set_drvdata(pdev, common);
795cc8bbe1aSYong Wu return 0;
796cc8bbe1aSYong Wu }
797cc8bbe1aSYong Wu
mtk_smi_common_remove(struct platform_device * pdev)798cc8bbe1aSYong Wu static int mtk_smi_common_remove(struct platform_device *pdev)
799cc8bbe1aSYong Wu {
80047404757SYong Wu struct mtk_smi *common = dev_get_drvdata(&pdev->dev);
80147404757SYong Wu
80247404757SYong Wu if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
80347404757SYong Wu device_link_remove(&pdev->dev, common->smi_common_dev);
804cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev);
805cc8bbe1aSYong Wu return 0;
806cc8bbe1aSYong Wu }
807cc8bbe1aSYong Wu
mtk_smi_common_resume(struct device * dev)8084f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_resume(struct device *dev)
8094f0a1a1aSYong Wu {
8104f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev);
811431e9cabSYong Wu const struct mtk_smi_reg_pair *init = common->plat->init;
812431e9cabSYong Wu u32 bus_sel = common->plat->bus_sel; /* default is 0 */
813431e9cabSYong Wu int ret, i;
8144f0a1a1aSYong Wu
8150e14917cSYong Wu ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
8160e14917cSYong Wu if (ret)
8174f0a1a1aSYong Wu return ret;
818567e58cfSYong Wu
819431e9cabSYong Wu if (common->plat->type != MTK_SMI_GEN2)
820431e9cabSYong Wu return 0;
821431e9cabSYong Wu
822431e9cabSYong Wu for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
823431e9cabSYong Wu writel_relaxed(init[i].value, common->base + init[i].offset);
824431e9cabSYong Wu
825567e58cfSYong Wu writel(bus_sel, common->base + SMI_BUS_SEL);
8264f0a1a1aSYong Wu return 0;
8274f0a1a1aSYong Wu }
8284f0a1a1aSYong Wu
mtk_smi_common_suspend(struct device * dev)8294f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
8304f0a1a1aSYong Wu {
8314f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev);
8324f0a1a1aSYong Wu
8330e14917cSYong Wu clk_bulk_disable_unprepare(common->clk_num, common->clks);
8344f0a1a1aSYong Wu return 0;
8354f0a1a1aSYong Wu }
8364f0a1a1aSYong Wu
8374f0a1a1aSYong Wu static const struct dev_pm_ops smi_common_pm_ops = {
8384f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
839fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
840fb03082aSYong Wu pm_runtime_force_resume)
8414f0a1a1aSYong Wu };
8424f0a1a1aSYong Wu
843cc8bbe1aSYong Wu static struct platform_driver mtk_smi_common_driver = {
844cc8bbe1aSYong Wu .probe = mtk_smi_common_probe,
845cc8bbe1aSYong Wu .remove = mtk_smi_common_remove,
846cc8bbe1aSYong Wu .driver = {
847cc8bbe1aSYong Wu .name = "mtk-smi-common",
848cc8bbe1aSYong Wu .of_match_table = mtk_smi_common_of_ids,
8494f0a1a1aSYong Wu .pm = &smi_common_pm_ops,
850cc8bbe1aSYong Wu }
851cc8bbe1aSYong Wu };
852cc8bbe1aSYong Wu
85318212031SYong Wu static struct platform_driver * const smidrivers[] = {
85418212031SYong Wu &mtk_smi_common_driver,
85518212031SYong Wu &mtk_smi_larb_driver,
85618212031SYong Wu };
85718212031SYong Wu
mtk_smi_init(void)858cc8bbe1aSYong Wu static int __init mtk_smi_init(void)
859cc8bbe1aSYong Wu {
86018212031SYong Wu return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
861cc8bbe1aSYong Wu }
8624f608d38SYong Wu module_init(mtk_smi_init);
86350fc8d92SYong Wu
mtk_smi_exit(void)86450fc8d92SYong Wu static void __exit mtk_smi_exit(void)
86550fc8d92SYong Wu {
86650fc8d92SYong Wu platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
86750fc8d92SYong Wu }
86850fc8d92SYong Wu module_exit(mtk_smi_exit);
86950fc8d92SYong Wu
87050fc8d92SYong Wu MODULE_DESCRIPTION("MediaTek SMI driver");
87150fc8d92SYong Wu MODULE_LICENSE("GPL v2");
872