11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2cc8bbe1aSYong Wu /* 3cc8bbe1aSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 4cc8bbe1aSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 5cc8bbe1aSYong Wu */ 6cc8bbe1aSYong Wu #ifndef MTK_IOMMU_SMI_H 7cc8bbe1aSYong Wu #define MTK_IOMMU_SMI_H 8cc8bbe1aSYong Wu 9cc8bbe1aSYong Wu #include <linux/bitops.h> 10cc8bbe1aSYong Wu #include <linux/device.h> 11cc8bbe1aSYong Wu 1250fc8d92SYong Wu #if IS_ENABLED(CONFIG_MTK_SMI) 13cc8bbe1aSYong Wu 144e508b25SChengci.Xu enum iommu_atf_cmd { 154e508b25SChengci.Xu IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to en/disable iommu */ 16*946e719cSChengci.Xu IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */ 174e508b25SChengci.Xu IOMMU_ATF_CMD_MAX, 184e508b25SChengci.Xu }; 194e508b25SChengci.Xu 20cc8bbe1aSYong Wu #define MTK_SMI_MMU_EN(port) BIT(port) 21cc8bbe1aSYong Wu 22cc8bbe1aSYong Wu struct mtk_smi_larb_iommu { 23cc8bbe1aSYong Wu struct device *dev; 24cc8bbe1aSYong Wu unsigned int mmu; 258d2c749eSYong Wu unsigned char bank[32]; 26cc8bbe1aSYong Wu }; 27cc8bbe1aSYong Wu 28cc8bbe1aSYong Wu #endif 29cc8bbe1aSYong Wu 30cc8bbe1aSYong Wu #endif 31