/openbmc/u-boot/arch/riscv/include/asm/ |
H A D | cache.h | 52923c6d Tue Nov 06 19:34:06 CST 2018 Rick Chen <rick@andestech.com> riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
/openbmc/u-boot/arch/riscv/cpu/ax25/ |
H A D | Kconfig | 52923c6d Tue Nov 06 19:34:06 CST 2018 Rick Chen <rick@andestech.com> riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
H A D | cpu.c | 52923c6d Tue Nov 06 19:34:06 CST 2018 Rick Chen <rick@andestech.com> riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
H A D | cache.c | 52923c6d Tue Nov 06 19:34:06 CST 2018 Rick Chen <rick@andestech.com> riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
H A D | Makefile | 52923c6d Tue Nov 06 19:34:06 CST 2018 Rick Chen <rick@andestech.com> riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
/openbmc/u-boot/arch/riscv/lib/ |
H A D | cache.c | 52923c6d Tue Nov 06 19:34:06 CST 2018 Rick Chen <rick@andestech.com> riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
/openbmc/u-boot/arch/riscv/cpu/ |
H A D | start.S | 52923c6d Tue Nov 06 19:34:06 CST 2018 Rick Chen <rick@andestech.com> riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|
/openbmc/u-boot/arch/riscv/ |
H A D | Kconfig | 52923c6d Tue Nov 06 19:34:06 CST 2018 Rick Chen <rick@andestech.com> riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
|