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Searched +full:zynqmp +full:- +full:dpdma (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxlnx,zynqmp-dpdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: ../dma-controller.yaml#
22 "#dma-cells":
25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
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/openbmc/linux/drivers/dma/xilinx/
H A Dxilinx_dpdma.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP DPDMA Engine driver
5 * Copyright (C) 2015 - 2020 Xilinx, Inc.
28 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
31 #include "../virt-dma.h"
33 /* DPDMA registers */
119 /* DPDMA descriptor fields */
142 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
180 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor
181 * @hw: DPDMA hardware descriptor
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
21 "#address-cells":
24 "#size-cells":
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/openbmc/qemu/include/hw/arm/
H A Dxlnx-zynqmp.h24 #include "hw/net/xlnx-zynqmp-can.h"
25 #include "hw/ide/ahci-sysbus.h"
29 #include "hw/dma/xlnx-zdma.h"
31 #include "hw/intc/xlnx-zynqmp-ipi.h"
32 #include "hw/rtc/xlnx-zynqmp-rtc.h"
38 #include "hw/nvram/xlnx-bbram.h"
39 #include "hw/nvram/xlnx-zynqmp-efuse.h"
40 #include "hw/or-irq.h"
41 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
42 #include "hw/misc/xlnx-zynqmp-crf.h"
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/openbmc/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_disp.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ZynqMP Display Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
24 /* The DPDMA is limited to 44 bit addressing. */
36 * enum zynqmp_dpsub_layer_id - Layer identifier
46 * enum zynqmp_dpsub_layer_mode - Layer mode
47 * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode
H A Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Display Controller Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 #include <linux/dma-mapping.h>
33 * --------
35 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
38 * +------------------------------------------------------------+
39 * +--------+ | +----------------+ +-----------+ |
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/openbmc/linux/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
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/openbmc/qemu/hw/arm/
H A Dxlnx-zynqmp.c21 #include "hw/arm/xlnx-zynqmp.h"
28 #include "target/arm/cpu-qom.h"
218 int num_rpus = MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), in xlnx_zynqmp_create_rpu()
222 /* Don't create rpu-cluster object if there's nothing to put in it */ in xlnx_zynqmp_create_rpu()
226 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, in xlnx_zynqmp_create_rpu()
228 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); in xlnx_zynqmp_create_rpu()
233 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", in xlnx_zynqmp_create_rpu()
234 &s->rpu_cpu[i], in xlnx_zynqmp_create_rpu()
235 ARM_CPU_TYPE_NAME("cortex-r5f")); in xlnx_zynqmp_create_rpu()
237 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); in xlnx_zynqmp_create_rpu()
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/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
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/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
16 compatible = "xlnx,zynqmp";
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
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/openbmc/linux/drivers/dma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
220 This module can be found on Freescale Vybrid and LS-1 SoCs.
263 Enable support for the IMG multi-threaded DMA controller (MDC).
283 tristate "Intel integrated DMA 64-bit support"
319 accel-config) to continue function. It is expected that accel-config
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/openbmc/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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H A Dopengrok2.0.log1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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