| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_hw_algo.c | 150 * The Vref register have non linear order. Need to check what will be in ddr3_tip_vref()
177 /* set vref as centralization pattern */ in ddr3_tip_vref()
196 ("VREF config, IF[ %d ]pup[ %d ] - Vref tune not requered (%d)\n", in ddr3_tip_vref()
211 ("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n", in ddr3_tip_vref()
288 ("I/F[ %d ], pup[ %d ] CHECK progress - Current %d Last %d, limit VREF %d (%d)\n", in ddr3_tip_vref()
306 * size (take the max) and Vref in ddr3_tip_vref()
314 * better Vref value in ddr3_tip_vref()
318 * Vref. in ddr3_tip_vref()
328 ("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n", in ddr3_tip_vref()
334 /* continue to update the Vref index */ in ddr3_tip_vref()
[all …]
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | st,stm32h7-rcc.txt | 70 Vref --------- --------
80 - VCO = ( Vref / DIVM ) * DIVN
83 - VCO = ( Vref / DIVM ) * ( DIVN + FRACN / 2^13)
108 - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz
109 - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz
110 - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz
111 - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz
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| /openbmc/u-boot/drivers/adc/ |
| H A D | stm32-adc-core.c | 149 ret = device_get_supply_regulator(dev, "vref-supply", &common->vref); in stm32_adc_core_probe()
151 dev_err(dev, "can't get vref-supply: %d\n", ret); in stm32_adc_core_probe()
155 ret = regulator_get_value(common->vref); in stm32_adc_core_probe()
157 dev_err(dev, "can't get vref-supply value: %d\n", ret); in stm32_adc_core_probe()
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| H A D | stm32-adc-core.h | 39 * @vref: regulator reference
47 struct udevice *vref; member
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| H A D | adc-uclass.c | 348 int ret, val, vref; in adc_raw_to_uV() local
351 ret = adc_vdd_value(dev, &vref); in adc_raw_to_uV()
356 vref -= val; in adc_raw_to_uV()
362 raw64 *= vref; in adc_raw_to_uV()
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| H A D | stm32-adc.c | 217 /* VDD supplied by common vref pin */ in stm32_adc_probe()
218 uc_pdata->vdd_supply = common->vref; in stm32_adc_probe()
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| /openbmc/qemu/include/hw/adc/ |
| H A D | npcm7xx_adc.h | 41 * @vref: The external reference voltage.
59 uint32_t vref; member
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| /openbmc/qemu/hw/adc/ |
| H A D | npcm7xx_adc.c | 99 ? s->iref : s->vref; in npcm7xx_adc_convert_done()
247 object_property_add_uint32_ptr(obj, "vref", in npcm7xx_adc_init()
248 &s->vref, OBJ_PROP_FLAG_WRITE); in npcm7xx_adc_init()
262 VMSTATE_UINT32(vref, NPCM7xxADCState),
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| /openbmc/qemu/tests/qtest/ |
| H A D | npcm7xx_adc-test.c | 146 adc_qom_set(qts, adc, "vref", value); in adc_write_vref()
236 uint32_t index, input, vref, output, expected_output; in test_convert_external() local
244 vref = vref_list[j]; in test_convert_external()
245 expected_output = adc_calculate_output(input, vref); in test_convert_external()
248 adc_write_vref(qts, adc, vref); in test_convert_external()
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| /openbmc/u-boot/arch/x86/cpu/quark/ |
| H A D | smc.h | 458 #define MIN_VREF_EYE 10 /* in VREF Codes */
461 /* how many VREF codes to jump while margining */
463 /* offset into "vref_codes[]" for minimum allowed VREF setting */
465 /* offset into "vref_codes[]" for maximum allowed VREF setting */
474 B, /* BOTTOM VREF */
475 T /* TOP VREF */
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| H A D | smc.c | 463 /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */ in ddrphy_init()
470 /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */ in ddrphy_init()
537 /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */ in ddrphy_init()
554 /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */ in ddrphy_init()
565 /* RCOMP Vref PU/PD */ in ddrphy_init()
569 /* RCOMP Vref PU/PD */ in ddrphy_init()
573 /* RCOMP Vref PU/PD */ in ddrphy_init()
577 /* RCOMP Vref PU/PD */ in ddrphy_init()
581 /* RCOMP Vref PU/PD */ in ddrphy_init()
591 /* ODT VREF = 1.5 x 274/360+274 = 0.65V (code of ~50) */ in ddrphy_init()
[all …]
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| H A D | mrc_util.h | 67 VREF, enumerator
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| /openbmc/u-boot/doc/device-tree-bindings/adc/ |
| H A D | st,stm32-adc.txt | 41 - vref-supply: Phandle to the vref input analog reference voltage.
103 vref-supply = <®_vref>;
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| /openbmc/u-boot/doc/device-tree-bindings/regulator/ |
| H A D | st,stm32-vrefbuf.txt | 5 components through the dedicated VREF+ pin.
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| /openbmc/u-boot/arch/x86/include/asm/arch-quark/ |
| H A D | mrc.h | 71 * Vref setting
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES]; member
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | stm32429i-eval.dts | 50 regulator-name = "vref";
117 vref-supply = <®_vref>;
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| H A D | imx6ul-pico-hobbit.dts | 76 vref-supply = <®_3p3v>;
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| H A D | sunxi-reference-design-tablet.dtsi | 61 vref-supply = <®_vcc3v0>;
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| H A D | sunxi-q8-common.dtsi | 61 vref-supply = <®_vcc3v0>;
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| H A D | sun6i-a31s-colorfly-e708-q1.dts | 53 vref-supply = <®_aldo3>;
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| H A D | sun6i-a31s-inet-q972.dts | 73 vref-supply = <®_aldo3>;
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| H A D | at91-sama5d4ek.dts | 114 /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
115 atmel,adc-vref = <3300>;
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| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | fsl_ddr_gen4.c | 222 /* DRAM VRef will not be trained */ in fsl_ddr_set_memctl_regs()
259 /* Disable DRAM VRef training */ in fsl_ddr_set_memctl_regs()
270 /* Enable Vref training */ in fsl_ddr_set_memctl_regs()
364 /* The vref setting sequence is different for range 2 */ in fsl_ddr_set_memctl_regs()
368 /* Set VREF */ in fsl_ddr_set_memctl_regs()
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| /openbmc/openbmc/meta-facebook/meta-bletchley/recipes-bletchley/motor-ctrl/files/ |
| H A D | motor-ctrl | 15 # 5. Value of Motor Driver VREF PIN
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| /openbmc/u-boot/board/st/stm32mp1/ |
| H A D | board.c | 74 /* Enable BUCK2 and VREF */ in board_ddr_power_init()
|