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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-st.txt1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
[all …]
H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
[all …]
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
[all …]
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
[all …]
H A Dbrcm,sdhci-brcmstb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Al Cooper <alcooperx@gmail.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
16 - items:
17 - enum:
18 - brcm,bcm7216-sdhci
19 - const: brcm,bcm7445-sdhci
[all …]
H A Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-dw-mshc
19 - samsung,exynos4412-dw-mshc
20 - samsung,exynos5250-dw-mshc
21 - samsung,exynos5420-dw-mshc
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam57xx-beagle-x15.dts2 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
9 #include "am57xx-beagle-x15-common.dtsi"
12 /* NOTE: This describes the "original" pre-production A2 revision */
13 model = "TI AM5728 BeagleBoard-X15";
23 pinctrl-names = "default", "hs";
24 pinctrl-0 = <&mmc1_pins_default>;
25 pinctrl-1 = <&mmc1_pins_hs>;
27 vmmc-supply = <&ldo1_reg>;
28 /delete-property/ sd-uhs-sdr104;
29 /delete-property/ sd-uhs-sdr50;
[all …]
H A Dstm32mp157c-ed1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 /dts-v1/;
9 #include "stm32mp157-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/mfd/st,stpmu1.h>
15 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
18 stdout-path = "serial3:115200n8";
25 sd_switch: regulator-sd_switch {
26 compatible = "regulator-gpio";
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstih410-b2120.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include "stihxxx-b2120.dtsi"
11 compatible = "st,stih410-b2120", "st,stih410";
14 stdout-path = &sbc_serial0;
38 max-frequency = <200000000>;
39 sd-uhs-sdr50;
40 sd-uhs-sdr104;
41 sd-uhs-ddr50;
60 sti-display-subsystem@0 {
[all …]
H A Dstih418-b2199.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2199", "st,stih418";
14 stdout-path = &sbc_serial0;
28 compatible = "gpio-leds";
29 led-red {
32 linux,default-trigger = "heartbeat";
34 led-green {
36 default-state = "off";
[all …]
H A Dstm32mp157c-ed1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxaa-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/mfd/st,stpmic1.h>
17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
24 stdout-path = "serial0:115200n8";
32 reserved-memory {
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxl-s905x-libretech-cc-v2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/sound/meson-aiu.h>
13 #include "meson-gxl-s905x.dtsi"
16 compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x",
17 "amlogic,meson-gxl";
18 model = "Libre Computer AML-S905X-CC V2";
27 stdout-path = "serial0:115200n8";
[all …]
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
H A Dmeson-gx-libretech-pc.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 /* Libretech Amlogic GX PC form factor - AKA: Tartiflette */
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/sound/meson-aiu.h>
14 adc-keys {
15 compatible = "adc-keys";
16 io-channels = <&saradc 0>;
17 io-channel-names = "buttons";
18 keyup-threshold-microvolt = <1800000>;
[all …]
H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/sound/meson-aiu.h>
15 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
16 model = "Hardkernel ODROID-C2";
24 stdout-path = "serial0:115200n8";
32 usb_otg_pwr: regulator-usb-pwrs {
33 compatible = "regulator-fixed";
[all …]
/openbmc/linux/drivers/mmc/core/
H A Dhost.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2007-2008 Pierre Ossman
25 #include <linux/mmc/slot-gpio.h>
30 #include "slot-gpio.h"
47 if (!host->bus_ops) in mmc_host_class_prepare()
51 if (host->bus_ops->pre_suspend) in mmc_host_class_prepare()
52 return host->bus_ops->pre_suspend(host); in mmc_host_class_prepare()
77 wakeup_source_unregister(host->ws); in mmc_host_classdev_release()
78 if (of_alias_get_id(host->parent->of_node, "mmc") < 0) in mmc_host_classdev_release()
79 ida_simple_remove(&mmc_host_ida, host->index); in mmc_host_classdev_release()
[all …]
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/fault-inject.h>
55 struct mmc_host *host = s->private; in mmc_ios_show()
56 struct mmc_ios *ios = &host->ios; in mmc_ios_show()
59 seq_printf(s, "clock:\t\t%u Hz\n", ios->clock); in mmc_ios_show()
60 if (host->actual_clock) in mmc_ios_show()
61 seq_printf(s, "actual clock:\t%u Hz\n", host->actual_clock); in mmc_ios_show()
62 seq_printf(s, "vdd:\t\t%u ", ios->vdd); in mmc_ios_show()
63 if ((1 << ios->vdd) & MMC_VDD_165_195) in mmc_ios_show()
64 seq_printf(s, "(1.65 - 1.95 V)\n"); in mmc_ios_show()
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0+
17 /* HRS - Host Register Set (specific to Cadence) */
37 /* SRS - Slot Register Set (SDHCI-compatible) */
55 * The tuned val register is 6 bit-wide, but not the whole of the range is
56 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
73 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
74 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
75 { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
76 { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
77 { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
[all …]
H A Dmmc-uclass.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dm/device-internal.h>
22 if (ops->send_cmd) in dm_mmc_send_cmd()
23 ret = ops->send_cmd(dev, cmd, data); in dm_mmc_send_cmd()
25 ret = -ENOSYS; in dm_mmc_send_cmd()
33 return dm_mmc_send_cmd(mmc->dev, cmd, data); in mmc_send_cmd()
40 if (!ops->set_ios) in dm_mmc_set_ios()
41 return -ENOSYS; in dm_mmc_set_ios()
42 return ops->set_ios(dev); in dm_mmc_set_ios()
47 return dm_mmc_set_ios(mmc->dev); in mmc_set_ios()
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-firefly-reload.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include "rk3288-firefly-reload-core.dtsi"
11 model = "Firefly-RK3288-reload";
12 compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
14 adc-keys {
15 compatible = "adc-keys";
16 io-channels = <&saradc 1>;
17 io-channel-names = "buttons";
18 keyup-threshold-microvolt = <1800000>;
[all …]
/openbmc/u-boot/include/
H A Dmvebu_mmc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Marvell MMC/SD/SDIO driver
7 * Written-by: Maen Suleiman, Gerald Kerma
217 /* Can do MMC high-speed timing */
219 /* Can do SD high-speed timing */
225 /* Needs polling for card-detection */
244 /* Host supports UHS SDR12 mode */
246 /* Host supports UHS SDR25 mode */
248 /* Host supports UHS SDR50 mode */
250 /* Host supports UHS SDR104 mode */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-skov-cpu.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
10 stdout-path = &uart2;
16 mdio-gpio0 = &mdio;
24 iio-hwmon {
25 compatible = "iio-hwmon";
26 io-channels = <&adc 0>, /* 24V */
31 compatible = "gpio-leds";
33 led-0 {
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 si5332_0: si5332-0 { /* u17 */
21 compatible = "fixed-clock";
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-phg.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "imx8mm-tqma8mqml.dtsi"
12 compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
20 stdout-path = &uart2;
24 compatible = "gpio-beeper";
25 pinctrl-0 = <&pinctrl_beeper>;
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_gpio_led>;
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "sdhci-pltfm.h"
19 /* HRS - Host Register Set (specific to Cadence) */
39 /* SRS - Slot Register Set (SDHCI-compatible) */
57 * The tuned val register is 6 bit-wide, but not the whole of the range is
58 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
90 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
91 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
92 { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
93 { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
[all …]

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