1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 23fe3b4fbSDrEagle /* 33fe3b4fbSDrEagle * Marvell MMC/SD/SDIO driver 43fe3b4fbSDrEagle * 53fe3b4fbSDrEagle * (C) Copyright 2012 63fe3b4fbSDrEagle * Marvell Semiconductor <www.marvell.com> 73fe3b4fbSDrEagle * Written-by: Maen Suleiman, Gerald Kerma 83fe3b4fbSDrEagle */ 93fe3b4fbSDrEagle 103fe3b4fbSDrEagle #ifndef __MVEBU_MMC_H__ 113fe3b4fbSDrEagle #define __MVEBU_MMC_H__ 123fe3b4fbSDrEagle 133fe3b4fbSDrEagle /* needed for the mmc_cfg definition */ 143fe3b4fbSDrEagle #include <mmc.h> 153fe3b4fbSDrEagle 163fe3b4fbSDrEagle #define MMC_BLOCK_SIZE 512 173fe3b4fbSDrEagle 183fe3b4fbSDrEagle /* 193fe3b4fbSDrEagle * Clock rates 203fe3b4fbSDrEagle */ 213fe3b4fbSDrEagle 223fe3b4fbSDrEagle #define MVEBU_MMC_CLOCKRATE_MAX 50000000 233fe3b4fbSDrEagle #define MVEBU_MMC_BASE_DIV_MAX 0x7ff 243fe3b4fbSDrEagle #define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK 253fe3b4fbSDrEagle #define MVEBU_MMC_BASE_FAST_CLK_100 100000000 263fe3b4fbSDrEagle #define MVEBU_MMC_BASE_FAST_CLK_200 200000000 273fe3b4fbSDrEagle 283fe3b4fbSDrEagle /* SDIO register */ 293fe3b4fbSDrEagle #define SDIO_SYS_ADDR_LOW 0x000 303fe3b4fbSDrEagle #define SDIO_SYS_ADDR_HI 0x004 313fe3b4fbSDrEagle #define SDIO_BLK_SIZE 0x008 323fe3b4fbSDrEagle #define SDIO_BLK_COUNT 0x00c 333fe3b4fbSDrEagle #define SDIO_ARG_LOW 0x010 343fe3b4fbSDrEagle #define SDIO_ARG_HI 0x014 353fe3b4fbSDrEagle #define SDIO_XFER_MODE 0x018 363fe3b4fbSDrEagle #define SDIO_CMD 0x01c 373fe3b4fbSDrEagle #define SDIO_RSP(i) (0x020 + ((i)<<2)) 383fe3b4fbSDrEagle #define SDIO_RSP0 0x020 393fe3b4fbSDrEagle #define SDIO_RSP1 0x024 403fe3b4fbSDrEagle #define SDIO_RSP2 0x028 413fe3b4fbSDrEagle #define SDIO_RSP3 0x02c 423fe3b4fbSDrEagle #define SDIO_RSP4 0x030 433fe3b4fbSDrEagle #define SDIO_RSP5 0x034 443fe3b4fbSDrEagle #define SDIO_RSP6 0x038 453fe3b4fbSDrEagle #define SDIO_RSP7 0x03c 463fe3b4fbSDrEagle #define SDIO_BUF_DATA_PORT 0x040 473fe3b4fbSDrEagle #define SDIO_RSVED 0x044 483fe3b4fbSDrEagle #define SDIO_HW_STATE 0x048 493fe3b4fbSDrEagle #define SDIO_PRESENT_STATE0 0x048 503fe3b4fbSDrEagle #define SDIO_PRESENT_STATE1 0x04c 513fe3b4fbSDrEagle #define SDIO_HOST_CTRL 0x050 523fe3b4fbSDrEagle #define SDIO_BLK_GAP_CTRL 0x054 533fe3b4fbSDrEagle #define SDIO_CLK_CTRL 0x058 543fe3b4fbSDrEagle #define SDIO_SW_RESET 0x05c 553fe3b4fbSDrEagle #define SDIO_NOR_INTR_STATUS 0x060 563fe3b4fbSDrEagle #define SDIO_ERR_INTR_STATUS 0x064 573fe3b4fbSDrEagle #define SDIO_NOR_STATUS_EN 0x068 583fe3b4fbSDrEagle #define SDIO_ERR_STATUS_EN 0x06c 593fe3b4fbSDrEagle #define SDIO_NOR_INTR_EN 0x070 603fe3b4fbSDrEagle #define SDIO_ERR_INTR_EN 0x074 613fe3b4fbSDrEagle #define SDIO_AUTOCMD12_ERR_STATUS 0x078 623fe3b4fbSDrEagle #define SDIO_CURR_BYTE_LEFT 0x07c 633fe3b4fbSDrEagle #define SDIO_CURR_BLK_LEFT 0x080 643fe3b4fbSDrEagle #define SDIO_AUTOCMD12_ARG_LOW 0x084 653fe3b4fbSDrEagle #define SDIO_AUTOCMD12_ARG_HI 0x088 663fe3b4fbSDrEagle #define SDIO_AUTOCMD12_INDEX 0x08c 673fe3b4fbSDrEagle #define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2)) 683fe3b4fbSDrEagle #define SDIO_AUTO_RSP0 0x090 693fe3b4fbSDrEagle #define SDIO_AUTO_RSP1 0x094 703fe3b4fbSDrEagle #define SDIO_AUTO_RSP2 0x098 713fe3b4fbSDrEagle #define SDIO_CLK_DIV 0x128 723fe3b4fbSDrEagle 733fe3b4fbSDrEagle #define WINDOW_CTRL(i) (0x108 + ((i) << 3)) 743fe3b4fbSDrEagle #define WINDOW_BASE(i) (0x10c + ((i) << 3)) 753fe3b4fbSDrEagle 763fe3b4fbSDrEagle /* SDIO_PRESENT_STATE */ 773fe3b4fbSDrEagle #define CARD_BUSY (1 << 1) 783fe3b4fbSDrEagle #define CMD_INHIBIT (1 << 0) 793fe3b4fbSDrEagle #define CMD_TXACTIVE (1 << 8) 803fe3b4fbSDrEagle #define CMD_RXACTIVE (1 << 9) 8128d27b79SGerald Kerma #define CMD_FIFO_EMPTY (1 << 13) 823fe3b4fbSDrEagle #define CMD_AUTOCMD12ACTIVE (1 << 14) 833fe3b4fbSDrEagle #define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \ 843fe3b4fbSDrEagle CMD_RXACTIVE | \ 853fe3b4fbSDrEagle CMD_TXACTIVE | \ 863fe3b4fbSDrEagle CMD_INHIBIT | \ 873fe3b4fbSDrEagle CARD_BUSY) 883fe3b4fbSDrEagle 893fe3b4fbSDrEagle /* 903fe3b4fbSDrEagle * SDIO_CMD 913fe3b4fbSDrEagle */ 923fe3b4fbSDrEagle 933fe3b4fbSDrEagle #define SDIO_CMD_RSP_NONE (0 << 0) 943fe3b4fbSDrEagle #define SDIO_CMD_RSP_136 (1 << 0) 953fe3b4fbSDrEagle #define SDIO_CMD_RSP_48 (2 << 0) 963fe3b4fbSDrEagle #define SDIO_CMD_RSP_48BUSY (3 << 0) 973fe3b4fbSDrEagle 983fe3b4fbSDrEagle #define SDIO_CMD_CHECK_DATACRC16 (1 << 2) 993fe3b4fbSDrEagle #define SDIO_CMD_CHECK_CMDCRC (1 << 3) 1003fe3b4fbSDrEagle #define SDIO_CMD_INDX_CHECK (1 << 4) 1013fe3b4fbSDrEagle #define SDIO_CMD_DATA_PRESENT (1 << 5) 1023fe3b4fbSDrEagle #define SDIO_UNEXPECTED_RESP (1 << 7) 1033fe3b4fbSDrEagle 1043fe3b4fbSDrEagle #define SDIO_CMD_INDEX(x) ((x) << 8) 1053fe3b4fbSDrEagle 1063fe3b4fbSDrEagle /* 1073fe3b4fbSDrEagle * SDIO_XFER_MODE 1083fe3b4fbSDrEagle */ 1093fe3b4fbSDrEagle 1103fe3b4fbSDrEagle #define SDIO_XFER_MODE_STOP_CLK (1 << 5) 1113fe3b4fbSDrEagle #define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1) 1123fe3b4fbSDrEagle #define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2) 1133fe3b4fbSDrEagle #define SDIO_XFER_MODE_INT_CHK_EN (1 << 3) 1143fe3b4fbSDrEagle #define SDIO_XFER_MODE_TO_HOST (1 << 4) 1153fe3b4fbSDrEagle #define SDIO_XFER_MODE_DMA (0 << 6) 1163fe3b4fbSDrEagle 1173fe3b4fbSDrEagle /* 1183fe3b4fbSDrEagle * SDIO_HOST_CTRL 1193fe3b4fbSDrEagle */ 1203fe3b4fbSDrEagle 1213fe3b4fbSDrEagle #define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0) 1223fe3b4fbSDrEagle 1233fe3b4fbSDrEagle #define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1) 1243fe3b4fbSDrEagle #define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1) 1253fe3b4fbSDrEagle #define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1) 1263fe3b4fbSDrEagle #define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1) 1273fe3b4fbSDrEagle #define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1) 1283fe3b4fbSDrEagle 1293fe3b4fbSDrEagle #define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3) 1303fe3b4fbSDrEagle #define SDIO_HOST_CTRL_LSB_FIRST (1 << 4) 1313fe3b4fbSDrEagle #define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9) 1323fe3b4fbSDrEagle #define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9) 1333fe3b4fbSDrEagle #define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10) 1343fe3b4fbSDrEagle 1353fe3b4fbSDrEagle #define SDIO_HOST_CTRL_TMOUT_MAX 0xf 1363fe3b4fbSDrEagle #define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11) 1373fe3b4fbSDrEagle #define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11) 1383fe3b4fbSDrEagle #define SDIO_HOST_CTRL_TMOUT_EN (1 << 15) 1393fe3b4fbSDrEagle 1403fe3b4fbSDrEagle /* 1413fe3b4fbSDrEagle * SDIO_SW_RESET 1423fe3b4fbSDrEagle */ 1433fe3b4fbSDrEagle 1443fe3b4fbSDrEagle #define SDIO_SW_RESET_NOW (1 << 8) 1453fe3b4fbSDrEagle 1463fe3b4fbSDrEagle /* 1473fe3b4fbSDrEagle * Normal interrupt status bits 1483fe3b4fbSDrEagle */ 1493fe3b4fbSDrEagle 1503fe3b4fbSDrEagle #define SDIO_NOR_ERROR (1 << 15) 1513fe3b4fbSDrEagle #define SDIO_NOR_UNEXP_RSP (1 << 14) 1523fe3b4fbSDrEagle #define SDIO_NOR_AUTOCMD12_DONE (1 << 13) 1533fe3b4fbSDrEagle #define SDIO_NOR_SUSPEND_ON (1 << 12) 1543fe3b4fbSDrEagle #define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11) 1553fe3b4fbSDrEagle #define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10) 1563fe3b4fbSDrEagle #define SDIO_NOR_READ_WAIT_ON (1 << 9) 1573fe3b4fbSDrEagle #define SDIO_NOR_CARD_INT (1 << 8) 1583fe3b4fbSDrEagle #define SDIO_NOR_READ_READY (1 << 5) 1593fe3b4fbSDrEagle #define SDIO_NOR_WRITE_READY (1 << 4) 1603fe3b4fbSDrEagle #define SDIO_NOR_DMA_INI (1 << 3) 1613fe3b4fbSDrEagle #define SDIO_NOR_BLK_GAP_EVT (1 << 2) 1623fe3b4fbSDrEagle #define SDIO_NOR_XFER_DONE (1 << 1) 1633fe3b4fbSDrEagle #define SDIO_NOR_CMD_DONE (1 << 0) 1643fe3b4fbSDrEagle 1653fe3b4fbSDrEagle /* 1663fe3b4fbSDrEagle * Error status bits 1673fe3b4fbSDrEagle */ 1683fe3b4fbSDrEagle 1693fe3b4fbSDrEagle #define SDIO_ERR_CRC_STATUS (1 << 14) 1703fe3b4fbSDrEagle #define SDIO_ERR_CRC_STARTBIT (1 << 13) 1713fe3b4fbSDrEagle #define SDIO_ERR_CRC_ENDBIT (1 << 12) 1723fe3b4fbSDrEagle #define SDIO_ERR_RESP_TBIT (1 << 11) 1733fe3b4fbSDrEagle #define SDIO_ERR_XFER_SIZE (1 << 10) 1743fe3b4fbSDrEagle #define SDIO_ERR_CMD_STARTBIT (1 << 9) 1753fe3b4fbSDrEagle #define SDIO_ERR_AUTOCMD12 (1 << 8) 1763fe3b4fbSDrEagle #define SDIO_ERR_DATA_ENDBIT (1 << 6) 1773fe3b4fbSDrEagle #define SDIO_ERR_DATA_CRC (1 << 5) 1783fe3b4fbSDrEagle #define SDIO_ERR_DATA_TIMEOUT (1 << 4) 1793fe3b4fbSDrEagle #define SDIO_ERR_CMD_INDEX (1 << 3) 1803fe3b4fbSDrEagle #define SDIO_ERR_CMD_ENDBIT (1 << 2) 1813fe3b4fbSDrEagle #define SDIO_ERR_CMD_CRC (1 << 1) 1823fe3b4fbSDrEagle #define SDIO_ERR_CMD_TIMEOUT (1 << 0) 1833fe3b4fbSDrEagle /* enable all for polling */ 1843fe3b4fbSDrEagle #define SDIO_POLL_MASK 0xffff 1853fe3b4fbSDrEagle 1863fe3b4fbSDrEagle /* 1873fe3b4fbSDrEagle * CMD12 error status bits 1883fe3b4fbSDrEagle */ 1893fe3b4fbSDrEagle 1903fe3b4fbSDrEagle #define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0) 1913fe3b4fbSDrEagle #define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1) 1923fe3b4fbSDrEagle #define SDIO_AUTOCMD12_ERR_CRC (1 << 2) 1933fe3b4fbSDrEagle #define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3) 1943fe3b4fbSDrEagle #define SDIO_AUTOCMD12_ERR_INDEX (1 << 4) 1953fe3b4fbSDrEagle #define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5) 1963fe3b4fbSDrEagle #define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6) 1973fe3b4fbSDrEagle 1983fe3b4fbSDrEagle #define MMC_RSP_PRESENT (1 << 0) 1993fe3b4fbSDrEagle /* 136 bit response */ 2003fe3b4fbSDrEagle #define MMC_RSP_136 (1 << 1) 2013fe3b4fbSDrEagle /* expect valid crc */ 2023fe3b4fbSDrEagle #define MMC_RSP_CRC (1 << 2) 2033fe3b4fbSDrEagle /* card may send busy */ 2043fe3b4fbSDrEagle #define MMC_RSP_BUSY (1 << 3) 2053fe3b4fbSDrEagle /* response contains opcode */ 2063fe3b4fbSDrEagle #define MMC_RSP_OPCODE (1 << 4) 2073fe3b4fbSDrEagle 2083fe3b4fbSDrEagle #define MMC_BUSMODE_OPENDRAIN 1 2093fe3b4fbSDrEagle #define MMC_BUSMODE_PUSHPULL 2 2103fe3b4fbSDrEagle 2113fe3b4fbSDrEagle #define MMC_BUS_WIDTH_1 0 2123fe3b4fbSDrEagle #define MMC_BUS_WIDTH_4 2 2133fe3b4fbSDrEagle #define MMC_BUS_WIDTH_8 3 2143fe3b4fbSDrEagle 2153fe3b4fbSDrEagle /* Can the host do 4 bit transfers */ 2163fe3b4fbSDrEagle #define MMC_CAP_4_BIT_DATA (1 << 0) 2173fe3b4fbSDrEagle /* Can do MMC high-speed timing */ 2183fe3b4fbSDrEagle #define MMC_CAP_MMC_HIGHSPEED (1 << 1) 2193fe3b4fbSDrEagle /* Can do SD high-speed timing */ 2203fe3b4fbSDrEagle #define MMC_CAP_SD_HIGHSPEED (1 << 2) 2213fe3b4fbSDrEagle /* Can signal pending SDIO IRQs */ 2223fe3b4fbSDrEagle #define MMC_CAP_SDIO_IRQ (1 << 3) 2233fe3b4fbSDrEagle /* Talks only SPI protocols */ 2243fe3b4fbSDrEagle #define MMC_CAP_SPI (1 << 4) 2253fe3b4fbSDrEagle /* Needs polling for card-detection */ 2263fe3b4fbSDrEagle #define MMC_CAP_NEEDS_POLL (1 << 5) 2273fe3b4fbSDrEagle /* Can the host do 8 bit transfers */ 2283fe3b4fbSDrEagle #define MMC_CAP_8_BIT_DATA (1 << 6) 2293fe3b4fbSDrEagle 2303fe3b4fbSDrEagle /* Nonremovable e.g. eMMC */ 2313fe3b4fbSDrEagle #define MMC_CAP_NONREMOVABLE (1 << 8) 2323fe3b4fbSDrEagle /* Waits while card is busy */ 2333fe3b4fbSDrEagle #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) 2343fe3b4fbSDrEagle /* Allow erase/trim commands */ 2353fe3b4fbSDrEagle #define MMC_CAP_ERASE (1 << 10) 2363fe3b4fbSDrEagle /* can support DDR mode at 1.8V */ 2373fe3b4fbSDrEagle #define MMC_CAP_1_8V_DDR (1 << 11) 2383fe3b4fbSDrEagle /* can support DDR mode at 1.2V */ 2393fe3b4fbSDrEagle #define MMC_CAP_1_2V_DDR (1 << 12) 2403fe3b4fbSDrEagle /* Can power off after boot */ 2413fe3b4fbSDrEagle #define MMC_CAP_POWER_OFF_CARD (1 << 13) 2423fe3b4fbSDrEagle /* CMD14/CMD19 bus width ok */ 2433fe3b4fbSDrEagle #define MMC_CAP_BUS_WIDTH_TEST (1 << 14) 2443fe3b4fbSDrEagle /* Host supports UHS SDR12 mode */ 2453fe3b4fbSDrEagle #define MMC_CAP_UHS_SDR12 (1 << 15) 2463fe3b4fbSDrEagle /* Host supports UHS SDR25 mode */ 2473fe3b4fbSDrEagle #define MMC_CAP_UHS_SDR25 (1 << 16) 2483fe3b4fbSDrEagle /* Host supports UHS SDR50 mode */ 2493fe3b4fbSDrEagle #define MMC_CAP_UHS_SDR50 (1 << 17) 2503fe3b4fbSDrEagle /* Host supports UHS SDR104 mode */ 2513fe3b4fbSDrEagle #define MMC_CAP_UHS_SDR104 (1 << 18) 2523fe3b4fbSDrEagle /* Host supports UHS DDR50 mode */ 2533fe3b4fbSDrEagle #define MMC_CAP_UHS_DDR50 (1 << 19) 2543fe3b4fbSDrEagle /* Host supports Driver Type A */ 2553fe3b4fbSDrEagle #define MMC_CAP_DRIVER_TYPE_A (1 << 23) 2563fe3b4fbSDrEagle /* Host supports Driver Type C */ 2573fe3b4fbSDrEagle #define MMC_CAP_DRIVER_TYPE_C (1 << 24) 2583fe3b4fbSDrEagle /* Host supports Driver Type D */ 2593fe3b4fbSDrEagle #define MMC_CAP_DRIVER_TYPE_D (1 << 25) 2603fe3b4fbSDrEagle /* CMD23 supported. */ 2613fe3b4fbSDrEagle #define MMC_CAP_CMD23 (1 << 30) 2623fe3b4fbSDrEagle /* Hardware reset */ 2633fe3b4fbSDrEagle #define MMC_CAP_HW_RESET (1 << 31) 2643fe3b4fbSDrEagle 2653fe3b4fbSDrEagle struct mvebu_mmc_cfg { 2663fe3b4fbSDrEagle u32 mvebu_mmc_base; 2673fe3b4fbSDrEagle u32 mvebu_mmc_clk; 2683fe3b4fbSDrEagle u8 max_bus_width; 2693fe3b4fbSDrEagle struct mmc_config cfg; 2703fe3b4fbSDrEagle }; 2713fe3b4fbSDrEagle 2723fe3b4fbSDrEagle /* 2733fe3b4fbSDrEagle * Functions prototypes 2743fe3b4fbSDrEagle */ 2753fe3b4fbSDrEagle 2763fe3b4fbSDrEagle int mvebu_mmc_init(bd_t *bis); 2773fe3b4fbSDrEagle 2783fe3b4fbSDrEagle #endif /* __MVEBU_MMC_H__ */ 279