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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
[all …]
/openbmc/linux/arch/s390/kernel/
H A Duprobes.c1 // SPDX-License-Identifier: GPL-2.0
3 * User-space Probes (UProbes) for s390
26 return probe_is_prohibited_opcode(auprobe->insn); in arch_uprobe_analyze_insn()
31 if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) in arch_uprobe_pre_xol()
32 return -EINVAL; in arch_uprobe_pre_xol()
33 if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) in arch_uprobe_pre_xol()
34 return -EINVAL; in arch_uprobe_pre_xol()
36 auprobe->saved_per = psw_bits(regs->psw).per; in arch_uprobe_pre_xol()
37 auprobe->saved_int_code = regs->int_code; in arch_uprobe_pre_xol()
38 regs->int_code = UPROBE_TRAP_NR; in arch_uprobe_pre_xol()
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/openbmc/linux/drivers/media/rc/
H A Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
37 #define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/
38 #define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */
42 #define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/
45 /* firmware RX pointer for new style buffer */
48 /* high parts of samples for fan input (8 samples)*/
52 #define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
66 /* fan as input settings */
80 #define ENE_CIRCFG_RX_EN 0x01 /* RX enable */
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/openbmc/linux/tools/spi/
H A Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
106 pabort("malformed input string"); in unescape()
118 static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len) in transfer() argument
124 .rx_buf = (unsigned long)rx, in transfer()
162 ret = write(out_fd, rx, len); in transfer()
170 hex_dump(rx, len, 32, "RX"); in transfer()
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/openbmc/u-boot/board/freescale/common/
H A Dvsc3316_3308.c1 // SPDX-License-Identifier: GPL-2.0+
31 " for 2-wire interface\n", vsc_addr); in vsc_if_enable()
33 /* enable 2-wire Serial InterFace (I2C) */ in vsc_if_enable()
58 return -ENODEV; in vsc3316_config()
63 printf("VSC:0x%x could not configured for 2-wire I/F.\n", in vsc3316_config()
68 /* config connections - page 0x00 */ in vsc3316_config()
72 * input to output */ in vsc3316_config()
76 /* input state - page 0x13 */ in vsc3316_config()
78 /* Configuring the required input of the switch */ in vsc3316_config()
82 /* Setting Global Input LOS threshold value */ in vsc3316_config()
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/openbmc/linux/arch/x86/crypto/
H A Dcast5-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast5 Cipher 16-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
14 .file "cast5-avx-x86_64-asm_64.S"
26 /* s-boxes */
33 16-way AVX cast5
46 #define RX %xmm8 macro
130 F_head(b1, RX, RGI1, RGI2, op0); \
131 F_head(b2, RX, RGI3, RGI4, op0); \
133 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
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H A Dcast6-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast6 Cipher 8-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
8 * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
13 #include "glue_helper-asm-avx.S"
15 .file "cast6-avx-x86_64-asm_64.S"
26 /* s-boxes */
33 8-way AVX cast6
47 #define RX %xmm8 macro
130 F_head(b1, RX, RGI1, RGI2, op0); \
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dnxp,imx8mq-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
14 NXP i.MX8MQ SoC. It handles the sensor/image input and process for all the
15 input imaging devices.
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/openbmc/linux/drivers/net/wan/
H A Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
68 #define RXS 0x16 /* RX Clock Source */
72 #define RRC 0x1A /* RX Ready Control */
77 /* Timer channel 0 (port 0 RX) registers - offset 0x60
78 Timer channel 1 (port 0 TX) registers - offset 0x68
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/openbmc/linux/arch/m68k/include/asm/
H A Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
35 #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
51 #define MCFUART_UIPR 0x34 /* Input Port (r) */
60 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
61 #define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
62 #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
63 #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
107 #define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
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/openbmc/linux/drivers/gpu/drm/amd/display/modules/hdcp/
H A Dhdcp1_transition.c30 struct mod_hdcp_transition_input_hdcp1 *input, in mod_hdcp_hdcp1_transition() argument
34 struct mod_hdcp_connection *conn = &hdcp->connection; in mod_hdcp_hdcp1_transition()
35 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp1_transition()
39 if (input->bksv_read != PASS || input->bcaps_read != PASS) { in mod_hdcp_hdcp1_transition()
40 /* 1A-04: repeatedly attempts on port access failure */ in mod_hdcp_hdcp1_transition()
49 if (input->create_session != PASS) { in mod_hdcp_hdcp1_transition()
51 adjust->hdcp1.disable = 1; in mod_hdcp_hdcp1_transition()
54 } else if (input->an_write != PASS || in mod_hdcp_hdcp1_transition()
55 input->aksv_write != PASS || in mod_hdcp_hdcp1_transition()
56 input->bksv_read != PASS || in mod_hdcp_hdcp1_transition()
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/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Dsystem_global.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 // SPDX-License-Identifier: GPL-2.0-or-later
15 * - The system is hetereogeneous; Multiple cells and devices classes
16 * - The cell and device instances are homogeneous, each device type
18 * - Device instances supporting a subset of the class capabilities are
25 * N.B. the 3 input formatters are of 2 different classess
40 * the bus for too long; as the input system can only buffer
41 * 2 lines on Moorefield and Cherrytrail, the input system buffers
128 IRQ1_ID, /* Input formatter */
129 IRQ2_ID, /* input system */
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/openbmc/linux/drivers/media/pci/cobalt/
H A Dcobalt-v4l2.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Derived from ivtv-ioctl.c and cx18-fileops.c
7 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include <linux/dma-mapping.h>
15 #include <linux/v4l2-dv-timings.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-event.h>
19 #include <media/v4l2-dv-timings.h>
23 #include "cobalt-alsa.h"
24 #include "cobalt-cpld.h"
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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dti,ds90ub960.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DS90UB9XX Family FPD-Link Deserializer Hubs
10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
13 The TI DS90UB9XX devices are FPD-Link video deserializers with I2C and GPIO
17 - $ref: /schemas/i2c/i2c-atr.yaml#
22 - ti,ds90ub960-q1
23 - ti,ds90ub9702-q1
33 clock-names:
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/openbmc/qemu/tests/qtest/fuzz/
H A Dvirtio_net_fuzz.c2 * virtio-net Fuzzing Target
10 * See the COPYING file in the top-level directory.
15 #include "standard-headers/linux/virtio_config.h"
17 #include "tests/qtest/libqos/virtio-net.h"
38 uint8_t rx; in virtio_net_fuzz_multi() member
46 QVirtioDevice *dev = net_if->vdev; in virtio_net_fuzz_multi()
52 Size -= sizeof(vqa); in virtio_net_fuzz_multi()
54 q = net_if->queues[vqa.queue % 3]; in virtio_net_fuzz_multi()
60 * backend. Otherwise, always place the input on a virtqueue. in virtio_net_fuzz_multi()
62 if (vqa.rx && sockfds_initialized) { in virtio_net_fuzz_multi()
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/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md18 …<https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-spec…
29 MCTP-compliant endpoints must accept.
31 ### IBF: Input Buffer Full
33 A hardware-defined flag bit in a KCS device's Status Register (STR). The IBF
35 Input Data Register (IDR).
37 ### IDR: Input Data Register
42 ### KCS: Keyboard-Controller-Style
48 systems. This interface is available built-in to several commercially available
49 microcontrollers. Data is transferred across the KCS interface using a per-byte
68 values larger than the BTU may improve throughput for data-intensive transfers.
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/openbmc/linux/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
58 /** @brief clock recovered from EAVB input */
126 /** @brief clock recovered from I2S1 input */
130 /** @brief clock recovered from I2S2 input */
134 /** @brief clock recovered from I2S3 input */
138 /** @brief clock recovered from I2S4 input */
142 /** @brief clock recovered from I2S5 input */
146 /** @brief clock recovered from I2S6 input */
192 /** @brief input from Tegra's XTAL_IN */
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/openbmc/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Minimum input (Tx) requests to be enqueued to ring doorbell */
22 /* Rx Queue: maximum descriptors per ring */
25 /* Rx buffer size: Use page size buffers.
28 * page buffers in consecutive Rx descriptors as fragments.
48 #define OCTEP_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN))
53 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
54 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
55 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
56 #define CFG_GET_IQ_PKIND(cfg) ((cfg)->iq.pkind)
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/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Datmel-ssc.txt4 - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
5 - atmel,at91rm9200-ssc: support pdc transfer
6 - atmel,at91sam9g45-ssc: support dma transfer
7 - reg: Should contain SSC registers location and length
8 - interrupts: Should contain SSC interrupt
9 - clock-names: tuple listing input clock names.
11 - clocks: phandles to input clocks.
14 Required properties for devices compatible with "atmel,at91sam9g45-ssc":
15 - dmas: DMA specifier, consisting of a phandle to DMA controller node,
16 the memory interface and SSC DMA channel ID (for tx and rx).
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/openbmc/linux/include/sound/
H A Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #define AK4114_REG_IO0 0x02 /* input/output control */
14 #define AK4114_REG_IO1 0x03 /* input/output control */
19 #define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */
20 #define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */
21 #define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */
22 #define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */
23 #define AK4114_REG_RXCSB4 0x0c /* RX channel status byte 4 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
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H A Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #define AK4117_REG_IO 0x02 /* input/output control */
18 #define AK4117_REG_RXCSB0 0x08 /* RX channel status byte 0 */
19 #define AK4117_REG_RXCSB1 0x09 /* RX channel status byte 1 */
20 #define AK4117_REG_RXCSB2 0x0a /* RX channel status byte 2 */
21 #define AK4117_REG_RXCSB3 0x0b /* RX channel status byte 3 */
22 #define AK4117_REG_RXCSB4 0x0c /* RX channel status byte 4 */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
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/openbmc/linux/drivers/staging/media/atomisp/pci/runtime/isys/interface/
H A Dia_css_isys.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2010 - 2015, Intel Corporation.
29 * Virtual Input System. (Input System 2401)
32 /* end of Virtual Input System */
44 * virtual streams are configured inside the input system. The CSI RX is
50 * @return 0 if successful, -EINVAL if
59 * virtual streams are configured inside the input system. The CSI RX is
65 * @return 0 if successful, -EINVAL if
100 * @param[in] input_format The input format.
105 * Translate an input format and mipi compression pair to the fmt_type.
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/openbmc/linux/crypto/
H A Dalgif_aead.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * algif_aead: User-space interface for AEAD algorithms
7 * This file provides the user-space API for AEAD ciphers.
11 * The kernel maintains two SGLs, the TX SGL and the RX SGL. The TX SGL is
14 * -- the data will only be tracked by the kernel. Upon receipt of one recvmsg
15 * call, the caller must provide a buffer which is tracked with the RX SGL.
21 * After the completion of the crypto operation, the RX SGL and the cipher
23 * the RX SGL release.
47 struct sock *psk = ask->parent; in aead_sufficient_data()
49 struct af_alg_ctx *ctx = ask->private; in aead_sufficient_data()
[all …]
/openbmc/linux/tools/testing/selftests/drivers/net/ocelot/
H A Dpsfp.sh2 # SPDX-License-Identifier: GPL-2.0
3 # Copyright 2021-2022 NXP
48 # Per-Stream Filtering and Policing filters
78 stats=$(tc -j -s filter show dev ${swp1} ingress chain $(PSFP) pref 1)
134 action gate base-time 0.000000000 \
135 sched-entry OPEN ${GATE_DURATION_NS} -1 -1 \
136 sched-entry CLOSE ${GATE_DURATION_NS} -1 -1
159 # Set up TC 6 for SO_TXTIME. tc-mqprio queues count from 1.
223 --input-file "${isochron_dat}" \
224 --printf-format "%u RX hw %T\n" \
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/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d27_wlsom1_ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
9 /dts-v1/;
10 #include "at91-sama5d27_wlsom1.dtsi"
11 #include <dt-bindings/input/input.h>
15 …compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel…
26 stdout-path = "serial0:115200n8";
29 gpio-keys {
30 compatible = "gpio-keys";
32 pinctrl-names = "default";
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