Lines Matching +full:rx +full:- +full:input
1 // SPDX-License-Identifier: GPL-2.0
3 * User-space Probes (UProbes) for s390
26 return probe_is_prohibited_opcode(auprobe->insn); in arch_uprobe_analyze_insn()
31 if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) in arch_uprobe_pre_xol()
32 return -EINVAL; in arch_uprobe_pre_xol()
33 if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) in arch_uprobe_pre_xol()
34 return -EINVAL; in arch_uprobe_pre_xol()
36 auprobe->saved_per = psw_bits(regs->psw).per; in arch_uprobe_pre_xol()
37 auprobe->saved_int_code = regs->int_code; in arch_uprobe_pre_xol()
38 regs->int_code = UPROBE_TRAP_NR; in arch_uprobe_pre_xol()
39 regs->psw.addr = current->utask->xol_vaddr; in arch_uprobe_pre_xol()
49 if (regs->int_code != UPROBE_TRAP_NR) in arch_uprobe_xol_was_trapped()
57 if (!(regs->psw.mask & PSW_MASK_PER)) in check_per_event()
71 regs->psw.addr >= current->thread.per_user.start && in check_per_event()
72 regs->psw.addr <= current->thread.per_user.end) in check_per_event()
80 int fixup = probe_get_fixup_type(auprobe->insn); in arch_uprobe_post_xol()
81 struct uprobe_task *utask = current->utask; in arch_uprobe_post_xol()
85 psw_bits(regs->psw).per = auprobe->saved_per; in arch_uprobe_post_xol()
86 regs->int_code = auprobe->saved_int_code; in arch_uprobe_post_xol()
89 regs->psw.addr += utask->vaddr - utask->xol_vaddr; in arch_uprobe_post_xol()
91 int reg = (auprobe->insn[0] & 0xf0) >> 4; in arch_uprobe_post_xol()
93 regs->gprs[reg] += utask->vaddr - utask->xol_vaddr; in arch_uprobe_post_xol()
96 int ilen = insn_length(auprobe->insn[0] >> 8); in arch_uprobe_post_xol()
98 if (regs->psw.addr - utask->xol_vaddr == ilen) in arch_uprobe_post_xol()
99 regs->psw.addr = utask->vaddr + ilen; in arch_uprobe_post_xol()
101 if (check_per_event(current->thread.per_event.cause, in arch_uprobe_post_xol()
102 current->thread.per_user.control, regs)) { in arch_uprobe_post_xol()
104 current->thread.per_event.address = utask->vaddr; in arch_uprobe_post_xol()
115 struct pt_regs *regs = args->regs; in arch_uprobe_exception_notify()
119 if (regs->int_code & 0x200) /* Trap during transaction */ in arch_uprobe_exception_notify()
139 regs->int_code = auprobe->saved_int_code; in arch_uprobe_abort_xol()
140 regs->psw.addr = current->utask->vaddr; in arch_uprobe_abort_xol()
141 current->thread.per_event.address = current->utask->vaddr; in arch_uprobe_abort_xol()
149 orig = regs->gprs[14]; in arch_uretprobe_hijack_return_addr()
150 regs->gprs[14] = trampoline; in arch_uretprobe_hijack_return_addr()
158 return user_stack_pointer(regs) <= ret->stack; in arch_uretprobe_is_alive()
160 return user_stack_pointer(regs) < ret->stack; in arch_uretprobe_is_alive()
167 psw->addr = __rewind_psw(*psw, -len); in adjust_psw_addr()
176 unsigned int mask = sizeof(*(ptr)) - 1; \
177 __typeof__(*(ptr)) input; \
182 else if (get_user(input, ptr)) \
185 *(output) = input; \
189 #define emu_store_ril(regs, ptr, input) \ argument
191 unsigned int mask = sizeof(*(ptr)) - 1; \
197 else if (put_user(*(input), __ptr)) \
208 unsigned int mask = sizeof(*(ptr)) - 1; \
209 __typeof__(*(ptr)) input; \
214 else if (get_user(input, ptr)) \
216 else if (input > *(cmp)) \
217 psw_bits((regs)->psw).cc = 1; \
218 else if (input < *(cmp)) \
219 psw_bits((regs)->psw).cc = 2; \
221 psw_bits((regs)->psw).cc = 0; \
247 if (!(regs->psw.mask & PSW_MASK_PER)) in sim_stor_event()
249 if (!(current->thread.per_user.control & PER_EVENT_STORE)) in sim_stor_event()
251 if ((void *)current->thread.per_user.start > (addr + len)) in sim_stor_event()
253 if ((void *)current->thread.per_user.end < addr) in sim_stor_event()
255 current->thread.per_event.address = regs->psw.addr; in sim_stor_event()
256 current->thread.per_event.cause = PER_EVENT_STORE >> 16; in sim_stor_event()
266 union split_register *rx; in handle_insn_ril() local
272 insn = (struct insn_ril *) &auprobe->insn; in handle_insn_ril()
273 rx = (union split_register *) ®s->gprs[insn->reg]; in handle_insn_ril()
274 uptr = (void *)(regs->psw.addr + (insn->disp * 2)); in handle_insn_ril()
275 ilen = insn_length(insn->opc0); in handle_insn_ril()
277 switch (insn->opc0) { in handle_insn_ril()
279 switch (insn->opc1) { in handle_insn_ril()
281 rx->u64 = (unsigned long)uptr; in handle_insn_ril()
286 switch (insn->opc1) { in handle_insn_ril()
288 rc = emu_load_ril((u16 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
291 rc = emu_load_ril((s16 __user *)uptr, &rx->u64); in handle_insn_ril()
294 rc = emu_load_ril((s16 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
297 rc = emu_load_ril((u16 __user *)uptr, &rx->u64); in handle_insn_ril()
300 rc = emu_load_ril((u64 __user *)uptr, &rx->u64); in handle_insn_ril()
303 rc = emu_load_ril((s32 __user *)uptr, &rx->u64); in handle_insn_ril()
306 rc = emu_load_ril((u32 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
309 rc = emu_load_ril((u32 __user *)uptr, &rx->u64); in handle_insn_ril()
312 rc = emu_store_ril(regs, (u16 __user *)uptr, &rx->u16[3]); in handle_insn_ril()
315 rc = emu_store_ril(regs, (u64 __user *)uptr, &rx->u64); in handle_insn_ril()
318 rc = emu_store_ril(regs, (u32 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
323 switch (insn->opc1) { in handle_insn_ril()
325 rc = emu_cmp_ril(regs, (s16 __user *)uptr, &rx->s64); in handle_insn_ril()
328 rc = emu_cmp_ril(regs, (s16 __user *)uptr, &rx->s32[1]); in handle_insn_ril()
331 rc = emu_cmp_ril(regs, (u16 __user *)uptr, &rx->u64); in handle_insn_ril()
334 rc = emu_cmp_ril(regs, (u16 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
337 rc = emu_cmp_ril(regs, (s64 __user *)uptr, &rx->s64); in handle_insn_ril()
340 rc = emu_cmp_ril(regs, (u64 __user *)uptr, &rx->u64); in handle_insn_ril()
343 rc = emu_cmp_ril(regs, (s32 __user *)uptr, &rx->s64); in handle_insn_ril()
346 rc = emu_cmp_ril(regs, (s32 __user *)uptr, &rx->s32[1]); in handle_insn_ril()
349 rc = emu_cmp_ril(regs, (u32 __user *)uptr, &rx->u64); in handle_insn_ril()
352 rc = emu_cmp_ril(regs, (u32 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
357 adjust_psw_addr(®s->psw, ilen); in handle_insn_ril()
360 regs->int_code = ilen << 16 | 0x0001; in handle_insn_ril()
364 regs->int_code = ilen << 16 | 0x0006; in handle_insn_ril()
368 regs->int_code = ilen << 16 | 0x0005; in handle_insn_ril()
376 if ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) || in arch_uprobe_skip_sstep()
377 ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) && in arch_uprobe_skip_sstep()
379 regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE); in arch_uprobe_skip_sstep()
383 if (probe_is_insn_relative_long(auprobe->insn)) { in arch_uprobe_skip_sstep()