Searched +full:r8a73a4 +full:- +full:div6 +full:- +full:clock (Results 1 – 4 of 4) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the r8a73a4 SoC9 #include <dt-bindings/clock/r8a73a4-clock.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/interrupt-controller/irq.h>14 compatible = "renesas,r8a73a4";15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;20 #address-cells = <1>;[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas CPG DIV6 Clock10 - Geert Uytterhoeven <geert+renesas@glider.be>13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse14 Generator (CPG). Their clock input is divided by a configurable factor from 120 - enum:21 - renesas,r8a73a4-div6-clock # R-Mobile APE6[all …]
1 # SPDX-License-Identifier: GPL-2.03 obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o4 obj-$(CONFIG_CLK_RZA1) += clk-rz.o5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o6 obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o7 obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o[all …]
1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)4 2024-1[all...]