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/openbmc/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1013
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 vcm-supply:
42 vcc-drv-supply:
[all …]
H A Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
38 vcm-supply:
40 Common-mode voltage regulator.
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/openbmc/linux/drivers/counter/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
31 tristate "ACCES 104-QUAD-8 driver"
37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature
38 encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).
41 operation on the respective count value attribute. The 104-QUAD-8
58 module will be called ftm-quaddec.
69 will be called intel-qep.
79 module will be called interrupt-cnt.
91 module will be called microchip-tcb-capture.
98 SoCs. This IP supports both 16-bit and 32-bit phase counting mode
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H A Dftm-quaddec.c1 // SPDX-License-Identifier: GPL-2.0
37 if (ftm->big_endian) in ftm_read()
38 *data = ioread32be(ftm->ftm_base + offset); in ftm_read()
40 *data = ioread32(ftm->ftm_base + offset); in ftm_read()
45 if (ftm->big_endian) in ftm_write()
46 iowrite32be(data, ftm->ftm_base + offset); in ftm_write()
48 iowrite32(data, ftm->ftm_base + offset); in ftm_write()
90 /* Select quad mode, reset other fields to zero */ in ftm_quaddec_init()
135 mutex_lock(&ftm->ftm_quaddec_mutex); in ftm_quaddec_set_prescaler()
144 mutex_unlock(&ftm->ftm_quaddec_mutex); in ftm_quaddec_set_prescaler()
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/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-bus.txt10 - #address-cells - number of cells required to define a chip select
12 - #size-cells - should be zero.
13 - compatible - name of SPI bus controller following generic names
15 - cs-gpios - (optional) gpios chip select.
20 flexible and non-standardized, it is left out of this binding with the
26 - num-cs : total number of chipselects
28 If cs-gpios is used the number of chip select will automatically increased
29 with max(cs-gpios > hw cs)
31 So if for example the controller has 2 CS lines, and the cs-gpios
34 cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Ddlg,da9121.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adam Ward <Adam.Ward.opensource@diasemi.com>
13 Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
14 Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
15 Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
16 Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
17 Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
18 Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
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/openbmc/linux/drivers/mtd/spi-nor/
H A Dsfdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i) ((i) - 1)
56 * Quad Enable Requirements (QER):
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
59 * instruction phase.
60 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
63 * Writing only one byte to the status register has the side-effect of
67 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
70 * - 011b: QE is bit 7 of status register 2. It is set via Write status
74 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mtd/spi-nor.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
60 switch (nor->cmd_ext_type) { in spi_nor_get_cmd_ext()
62 return ~op->cmd.opcode; in spi_nor_get_cmd_ext()
65 return op->cmd.opcode; in spi_nor_get_cmd_ext()
68 dev_err(nor->dev, "Unknown command extension type\n"); in spi_nor_get_cmd_ext()
74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
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/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
116 return -EINVAL; in ice_ptp_set_sma_config_e810t()
121 return -EINVAL; in ice_ptp_set_sma_config_e810t()
193 struct ice_hw *hw = &pf->hw; in ice_ptp_set_sma_e810t()
197 return -EOPNOTSUPP; in ice_ptp_set_sma_e810t()
237 return -EOPNOTSUPP; in ice_verify_pin_e810t()
245 return -EOPNOTSUPP; in ice_verify_pin_e810t()
249 return -EOPNOTSUPP; in ice_verify_pin_e810t()
252 return -EOPNOTSUPP; in ice_verify_pin_e810t()
259 * ice_set_tx_tstamp - Enable or disable Tx timestamping
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/openbmc/linux/drivers/spi/
H A Dspi-falcon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #define DRV_NAME "sflash-falcon"
43 /* Dummy Phase Length */
52 /* SCK Rise-edge Position */
58 /* SCK Fall-edge Position */
82 /* 8-bit multiplexed */
100 struct device *dev = &spi->dev; in falcon_sflash_xfer()
101 struct falcon_sflash *priv = spi_controller_get_devdata(spi->controller); in falcon_sflash_xfer()
102 const u8 *txp = t->tx_buf; in falcon_sflash_xfer()
103 u8 *rxp = t->rx_buf; in falcon_sflash_xfer()
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H A Dspi-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * 2002-2007 (c) MontaVista Software, Inc.
56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
120 if (!xspi->tx_ptr) { in xilinx_spi_tx()
121 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
125 switch (xspi->bytes_per_word) { in xilinx_spi_tx()
127 data = *(u8 *)(xspi->tx_ptr); in xilinx_spi_tx()
130 data = *(u16 *)(xspi->tx_ptr); in xilinx_spi_tx()
133 data = *(u32 *)(xspi->tx_ptr); in xilinx_spi_tx()
137 xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
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H A Dspi-rspi.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
41 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
69 /* SPCR - Control Register */
78 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
79 /* QSPI on R-Car Gen2 only */
80 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
81 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
83 /* SSLP - Slave Select Polarity Register */
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H A Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
161 * struct qspi_platform_data - zynqmp qspi platform data structure
169 * struct zynqmp_qspi - Defines qspi driver instance
215 * zynqmp_gqspi_read - For GQSPI controller read operation
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/openbmc/linux/Documentation/hwmon/
H A Dltc2978.rst10 Addresses scanned: -
18 Addresses scanned: -
26 Addresses scanned: -
34 Addresses scanned: -
42 Addresses scanned: -
52 Addresses scanned: -
60 Addresses scanned: -
68 Addresses scanned: -
76 Addresses scanned: -
84 Addresses scanned: -
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/openbmc/linux/tools/spi/
H A Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
175 printf("Usage: %s [-2348CDFHILMNORSZbdilopsv]\n", prog); in print_usage()
177 " -D --device device to use (default /dev/spidev1.1)\n" in print_usage()
178 " -s --speed max speed (Hz)\n" in print_usage()
179 " -d --delay delay (usec)\n" in print_usage()
180 " -l --loop loopback\n" in print_usage()
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/openbmc/u-boot/drivers/mtd/spi/
H A Dspi-nor-core.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/mtd/spi-nor.h>
21 #include <spi-mem.h>
29 * For everything but full-chip erase; probably could be much smaller, but kept
38 * spi_nor_setup_op() - Set up common properties of a spi-mem op.
48 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto); in spi_nor_setup_op()
50 if (op->addr.nbytes) in spi_nor_setup_op()
51 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto); in spi_nor_setup_op()
53 if (op->dummy.nbytes) in spi_nor_setup_op()
54 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto); in spi_nor_setup_op()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dzynq_qspi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
25 #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
35 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
36 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
37 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
38 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
101 struct zynq_qspi_platdata *plat = bus->platdata; in zynq_qspi_ofdata_to_platdata()
102 const void *blob = gd->fdt_blob; in zynq_qspi_ofdata_to_platdata()
105 plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob, in zynq_qspi_ofdata_to_platdata()
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H A Dzynqmp_gqspi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
176 struct zynqmp_qspi_platdata *plat = bus->platdata; in zynqmp_qspi_ofdata_to_platdata()
180 plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) + in zynqmp_qspi_ofdata_to_platdata()
182 plat->dma_regs = (struct zynqmp_qspi_dma_regs *) in zynqmp_qspi_ofdata_to_platdata()
191 struct zynqmp_qspi_regs *regs = priv->regs; in zynqmp_qspi_init_hw()
193 writel(GQSPI_GFIFO_SELECT, &regs->gqspisel); in zynqmp_qspi_init_hw()
194 writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr); in zynqmp_qspi_init_hw()
195 writel(GQSPI_FIFO_THRESHOLD, &regs->txftr); in zynqmp_qspi_init_hw()
196 writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr); in zynqmp_qspi_init_hw()
[all …]
/openbmc/linux/drivers/usb/gadget/udc/cdns2/
H A Dcdns2-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * USBHS-DEV device controller driver header file
14 #include <linux/dma-direction.h>
22 * struct cdns2_ep0_regs - endpoint 0 related registers.
45 /* EP0CS - bitmasks. */
54 /* Send STALL in the data stage phase. */
59 /* EP0FIFO - bitmasks. */
70 * struct cdns2_epx_base - base endpoint registers.
87 /* rxcon/txcon - endpoint control register bitmasks. */
88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
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/openbmc/u-boot/include/
H A DSA-1100.h2 * FILE SA-1100.h
8 * System StrongARM SA-1100
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
13 * StrongARM SA-1100 data sheet version 2.2.
15 * Language-specific definitions are selected by the
33 #include <asm/arch-sa1100/bitfield.h>
43 typedef Word Quad [4] ; typedef
81 typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
98 typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
110 typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
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/openbmc/linux/arch/x86/crypto/
H A Daesni-intel_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Implement AES algorithm in Intel AES-NI instructions.
5 * The white paper of AES-NI instructions can be downloaded from:
6 * http://softwarecommunity.intel.com/isn/downloads/intelavx/AES-Instructions-Set_WP.pdf
13 * Added RFC4106 AES-GCM support for 128-bit keys under the AEAD
14 * interface for 64-bit kernels.
30 #include <asm/nospec-branch.h>
35 * movaps (move aligned packed single) or integer use movdqa (move double quad
248 # Clobbers rax, r10-r13 and xmm0-xmm6, %xmm13
274 # Clobbers rax, r10-r13, and xmm0-xmm15
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/openbmc/openbmc/poky/bitbake/doc/bitbake-user-manual/
H A Dbitbake-user-manual-execution.rst1 .. SPDX-License-Identifier: CC-BY-2.5
11 development kit, or even a full, board-specific bootable Linux image,
25 <bitbake-user-manual-command>`" section.
40 the number of processors, which takes into account hyper-threading.
41 Thus, a quad-core build host with hyper-threading most likely shows
57 - **Recipes:** Details about particular pieces of software.
59 - **Class Data:** An abstraction of common build information (e.g. how to
62 - **Configuration Data:** Machine-specific settings, policy decisions,
82 - :term:`BB_ENV_PASSTHROUGH`
83 - :term:`BB_ENV_PASSTHROUGH_ADDITIONS`
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/openbmc/linux/sound/usb/
H A Dquirks-table.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
72 #define QUIRK_COMPOSITE_END { .ifnum = -1 }
127 /* Creative BT-D1 */
146 /* E-Mu 0202 USB */
148 /* E-Mu 0404 USB */
150 /* E-Mu Tracker Pre */
152 /* E-Mu 0204 USB */
214 * Logitech QuickCam: bDeviceClass is vendor-specific, so generic interface
256 YAMAHA_DEVICE(0x100c, "UC-MX"),
257 YAMAHA_DEVICE(0x100d, "UC-KX"),
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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-ibm-blueridge.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /dts-v1/;
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/i2c/i2c.h>
7 #include <dt-bindings/leds/leds-pca955x.h>
8 #include "aspeed-g6.dtsi"
9 #include "ibm-power11-quad.dtsi"
13 compatible = "ibm,blueridge-bmc", "aspeed,ast2600";
35 stdout-path = &uart5;
43 reserved-memory {
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/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
200 "BriefDescription": "Read-write data cache collisions"
210 …phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtrac…
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
395 …-word boundary, which causes it to require an additional slice than than what normally would be re…
430 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
450 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
455 "BriefDescription": "D-side L2 MRU touch commands sent to the L2"
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