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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dfsl,spi-fsl-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Han Xu <han.xu@nxp.com>
13 - $ref: spi-controller.yaml#
18 - enum:
19 - fsl,vf610-qspi
20 - fsl,imx6sx-qspi
21 - fsl,imx7d-qspi
[all …]
/openbmc/u-boot/board/freescale/ls1021aiot/
H A DREADME2 --------
3 The LS1021A-IOT is a Freescale reference board that hosts
4 the LS1021A SoC.
7 -------------------------
8 - DDR Controller
9 - Supports 1GB un-buffered DDR3L SDRAM discrete
10 devices(32-bit bus) with 4 bit ECC
11 - DDR power supplies 1.35V to all devices with
13 - Soldered DDR chip
14 - Supprot one fixed speed
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dls1021a-iot.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale ls1021a IOT board device tree source
9 #include "ls1021a.dtsi"
12 model = "LS1021A IOT Board";
15 enet2-rgmii-phy = &rgmii_phy1;
16 enet0-sgmii-phy = &sgmii_phy2;
17 enet1-sgmii-phy = &sgmii_phy0;
18 spi0 = &qspi;
23 &qspi {
24 bus-num = <0>;
[all …]
H A Dls1021a-twr.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale ls1021a TWR board common device tree source
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
8 #include "ls1021a.dtsi"
11 model = "LS1021A TWR Board";
14 enet2-rgmii-phy = &rgmii_phy1;
15 enet0-sgmii-phy = &sgmii_phy2;
16 enet1-sgmii-phy = &sgmii_phy0;
17 spi0 = &qspi;
22 stdout-path = &uart0;
[all …]
H A Dls1021a-qds.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale ls1021a QDS board common device tree source
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
8 #include "ls1021a.dtsi"
11 model = "LS1021A QDS Board";
14 enet0-rgmii-phy = &rgmii_phy1;
15 enet1-rgmii-phy = &rgmii_phy2;
16 enet2-rgmii-phy = &rgmii_phy3;
17 enet0-sgmii-phy = &sgmii_phy1c;
18 enet1-sgmii-phy = &sgmii_phy1d;
[all …]
H A Dls1021a.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale ls1021a SOC common device tree source
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "fsl,ls1021a";
13 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a7";
37 compatible = "arm,cortex-a7";
[all …]
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright (C) 2014-2015, Freescale Semiconductor
14 interrupt-parent = <&gic>;
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <100000000>;
20 clock-output-names = "sysclk";
23 gic: interrupt-controller@1400000 {
24 compatible = "arm,gic-400";
[all …]
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
14 interrupt-parent = <&gic>;
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <100000000>;
20 clock-output-names = "sysclk";
23 gic: interrupt-controller@1400000 {
24 compatible = "arm,gic-400";
25 #interrupt-cells = <3>;
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0+
3 dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb
4 dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
5 dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
6 dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
8 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
9 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
10 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
11 exynos4210-smdkv310.dtb \
12 exynos4210-universal_c210.dtb \
[all …]
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME2 --------
3 The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC.
5 LS1021A SoC Overview
6 ------------------
7 The QorIQ LS1 family, which includes the LS1021A communications processor,
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
[all …]
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
3 The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC.
5 LS1021A SoC Overview
6 ------------------
7 The QorIQ LS1 family, which includes the LS1021A communications processor,
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tqmls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
5 * D-82229 Seefeld, Germany.
9 #include "ls1021a.dtsi"
13 compatible = "tq,ls1021a-tqmls1021a", "fsl,ls1021a";
15 reg_3p3v_som: regulator-3p3v-som {
16 compatible = "regulator-fixed";
17 regulator-name = "3P3V_SOM";
18 regulator-min-microvolt = <3300000>;
[all …]
H A Dls1021a-iot.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2021-2022 NXP
7 /dts-v1/;
8 #include "ls1021a.dtsi"
11 model = "LS1021A-IOT Board";
12 compatible = "fsl,ls1021a-iot", "fsl,ls1021a";
14 sys_mclk: clock-mclk {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <24576000>;
[all …]
H A Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
[all …]
H A Dls1021a-twr.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 /dts-v1/;
8 #include "ls1021a.dtsi"
11 model = "LS1021A TWR Board";
12 compatible = "fsl,ls1021a-twr", "fsl,ls1021a";
20 sys_mclk: clock-mclk {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24576000>;
[all …]
H A Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
7 #include "ls1021a.dtsi"
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24576000>;
[all …]
H A Dls1021a-moxa-uc-8410a.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/
10 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include "ls1021a.dtsi"
17 model = "Moxa UC-8410A";
18 compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a";
26 sys_mclk: clock-mclk {
27 compatible = "fixed-clock";
[all …]
H A Dls1021a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 /dts-v1/;
8 #include "ls1021a.dtsi"
11 model = "LS1021A QDS Board";
12 compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
22 sys_mclk: clock-mclk {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <24576000>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dconfig.h1 /* SPDX-License-Identifier: GPL-2.0+ */
114 #define FSL_QSPI_COMPAT "fsl,ls1021a-qspi"
115 #define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi"
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
[all …]
/openbmc/u-boot/include/configs/
H A Dls1021aiot.h1 /* SPDX-License-Identifier: GPL-2.0+ */
136 /* QSPI */
182 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
218 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/openbmc/linux/drivers/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
145 supports spi-mem interface.
224 this code to manage the per-word or per-transfer accesses to the
253 Cadence QSPI is a specialized controller for connecting an SPI
254 Flash over 1/2/4-bit wide bus. Enable this option if you have a
255 device with a Cadence QSPI controller and want to access the
[all …]
H A Dspi-fsl-qspi.c1 // SPDX-License-Identifier: GPL-2.0+
18 * Based on the original fsl-quadspi.c SPI NOR driver:
42 #include <linux/spi/spi-mem.h>
158 #define LUT_PAD(x) (fls(x) - 1)
164 * ---------------------------------------------------
166 * ---------------------------------------------------
279 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; in needs_swap_endian()
284 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; in needs_4x_clock()
289 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; in needs_fill_txfifo()
294 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; in needs_wakeup_wait_mode()
[all …]

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