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/openbmc/linux/sound/soc/intel/catpt/
H A Dipc.c150 struct catpt_notify_glitch glitch; in catpt_dsp_notify_stream() local
168 memcpy_fromio(&glitch, catpt_inbox_addr(cdev), sizeof(glitch)); in catpt_dsp_notify_stream()
169 trace_catpt_ipc_payload((u8 *)&glitch, sizeof(glitch)); in catpt_dsp_notify_stream()
171 dev_warn(cdev->dev, "glitch %d at pos: 0x%08llx, wp: 0x%08x\n", in catpt_dsp_notify_stream()
172 glitch.type, glitch.presentation_pos, in catpt_dsp_notify_stream()
173 glitch.write_pos); in catpt_dsp_notify_stream()
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-at91.h18 #define PIO_IFER 0x20 /* Glitch Input Filter Enable */
19 #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
20 #define PIO_IFSR 0x28 /* Glitch Input Filter Status */
/openbmc/u-boot/arch/x86/include/asm/arch-braswell/
H A Dgpio.h180 int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \ argument
183 (((glitch) != NA) ? (glitch << 26) : 0) | \
191 (((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gxl-mali.dtsi29 * MALI_0 and MALI_1 muxed to a single clock by a glitch
35 <&clkc CLKID_MALI>; /* Glitch free mux */
H A Dmeson-gxbb.dtsi247 * MALI_0 and MALI_1 muxed to a single clock by a glitch
253 <&clkc CLKID_MALI>; /* Glitch free mux */
680 * VPU_0 and VPU_1 muxed to a single clock by a glitch
682 * Same for VAPB but with a final gate after the glitch free mux.
686 <&clkc CLKID_VPU>, /* Glitch free mux */
689 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
H A Dmeson-gxl.dtsi681 * VPU_0 and VPU_1 muxed to a single clock by a glitch
683 * Same for VAPB but with a final gate after the glitch free mux.
687 <&clkc CLKID_VPU>, /* Glitch free mux */
690 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
/openbmc/u-boot/doc/device-tree-bindings/leds/
H A Dleds-gpio.txt20 glitch should be produced where the LED momentarily turns off (or
22 state is, without producing a glitch. The default is off if this
/openbmc/linux/drivers/clk/qcom/
H A Dclk-rcg.h99 * struct clk_dyn_rcg - root clock generator with glitch free mux
101 * @mux_sel_bit: bit to switch glitch free mux
104 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
/openbmc/linux/drivers/iio/adc/
H A Dad7606_par.c31 * become unaligned, but some glitch or electrostatic discharge might in ad7606_par16_read_block()
65 * become unaligned, but some glitch or electrostatic discharge might in ad7606_par8_read_block()
/openbmc/linux/drivers/rtc/
H A Drtc-mxc_v2.c16 #define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
34 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
313 /* initialize glitch detect */ in mxc_rtc_probe()
/openbmc/linux/arch/arm/mach-s3c/
H A Dpm-gpio.c108 * { OUT => SFN } Change CON first, so new data will not glitch
109 * { OUT => IN } Change CON first, so new data will not glitch
111 * { SFN => OUT } Change DAT first, so new data will not glitch [1]
H A Dpm.h80 * that we do not glitch the state of the pins from that the bootloader's
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb.dtsi763 * VPU_0 and VPU_1 muxed to a single clock by a glitch
765 * Same for VAPB but with a final gate after the glitch free mux.
769 <&clkc CLKID_VPU>, /* Glitch free mux */
772 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
H A Dmeson-gxl.dtsi833 * VPU_0 and VPU_1 muxed to a single clock by a glitch
835 * Same for VAPB but with a final gate after the glitch free mux.
839 <&clkc CLKID_VPU>, /* Glitch free mux */
842 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
/openbmc/linux/Documentation/hwmon/
H A Daspeed-g6-pwm-tach.rst25 affected by fan signal glitch.
/openbmc/linux/include/linux/pinctrl/
H A Dpinctrl-state.h19 * glitch the pins. In those cases you can add an "init" pinctrl
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,audiocc-sm8250.yaml32 - description: Glitch Free Mux register clock
H A Dqcom,aoncc-sm8250.yaml32 - description: Glitch Free Mux register clock
/openbmc/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-nomadik.c384 bool glitch) in __nmk_gpio_set_mode_safe() argument
389 if (glitch && nmk_chip->set_ioforce) { in __nmk_gpio_set_mode_safe()
401 if (glitch && nmk_chip->set_ioforce) { in __nmk_gpio_set_mode_safe()
1534 bool glitch; in nmk_pmx_set() local
1566 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); in nmk_pmx_set()
1568 if (glitch) { in nmk_pmx_set()
1610 (g->altsetting & NMK_GPIO_ALT_C), glitch); in nmk_pmx_set()
1630 if (glitch) { in nmk_pmx_set()
1662 /* There is no glitch when converting any pin to GPIO */ in nmk_gpio_request_enable()
1776 /* No glitch when going to GPIO mode */ in nmk_pin_config_set()
/openbmc/linux/Documentation/devicetree/bindings/leds/
H A Dcommon.yaml65 default-state property is set the to same value, then no glitch should be
68 glitch.
/openbmc/linux/include/dt-bindings/pinctrl/
H A Ddra.h30 /* Certain pins need virtual mode, but note: they may glitch */
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Ddra.h33 /* Certain pins need virtual mode, but note: they may glitch */
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-class-mei90 The ME FW writes Glitch Detection HW (TRC)
/openbmc/u-boot/drivers/gpio/
H A Daltera_pio.c48 /* change the data first, then the direction. to avoid glitch */ in altera_pio_direction_output()
/openbmc/linux/drivers/hwmon/pmbus/
H A Ddelta-ahe50dc-fan.c23 * system's power outputs experience a glitch. in ahe50dc_fan_write_byte()

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