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/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dcavium-compact-flash.txt1 * Compact Flash
3 The Cavium Compact Flash device is connected to the Octeon Boot Bus,
5 industry standard compact flash devices.
8 - compatible: "cavium,ebt3000-compact-flash";
12 - reg: The base address of the CF chip select banks. Depending on
15 - cavium,bus-width: The width of the connection to the CF devices. Valid
18 - cavium,true-ide: Optional, if present the CF connection is in True IDE mode.
20 - cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
24 compact-flash@5,0 {
25 compatible = "cavium,ebt3000-compact-flash";
[all …]
H A Dpata-arasan.txt1 * ARASAN PATA COMPACT FLASH CONTROLLER
4 - compatible: "arasan,cf-spear1340"
5 - reg: Address range of the CF registers
6 - interrupt: Should contain the CF interrupt number
7 - clock-frequency: Interface clock rate, in Hz, one of
21 - arasan,broken-udma: if present, UDMA mode is unusable
22 - arasan,broken-mwdma: if present, MWDMA mode is unusable
23 - arasan,broken-pio: if present, PIO mode is unusable
24 - dmas: one DMA channel, as described in bindings/dma/dma.txt
26 - dma-names: the corresponding channel name, must be "data"
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dlpc32xx_nand_slc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * LPC32xx SLC NAND flash controller driver
5 * (C) Copyright 2015-2018 Vladimir Zapolskiy <vz@mleia.com>
21 #include <asm/arch/dma.h>
44 #define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
46 #define CFG_DMA_BURST (1 << 2) /* DMA burst bit */
47 #define CFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
52 #define CTRL_DMA_START (1 << 0) /* Start DMA channel bit */
55 #define STAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
87 * DMA Descriptors
[all …]
H A Dmxs_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 NAND flash driver
9 * Freescale GPMI NFC NAND Flash Driver
24 #include <asm/arch/imx-regs.h>
25 #include <asm/mach-imx/regs-bch.h>
26 #include <asm/mach-imx/regs-gpmi.h>
56 uint32_t addr = (uint32_t)info->data_buf; in mxs_nand_flush_data_buf()
58 flush_dcache_range(addr, addr + info->data_buf_size); in mxs_nand_flush_data_buf()
63 uint32_t addr = (uint32_t)info->data_buf; in mxs_nand_inval_data_buf()
65 invalidate_dcache_range(addr, addr + info->data_buf_size); in mxs_nand_inval_data_buf()
[all …]
/openbmc/linux/drivers/thunderbolt/
H A Ddma_port.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt DMA configuration based mailbox support
48 * struct tb_dma_port - DMA control port
49 * @sw: Switch the DMA port belongs to
50 * @port: Switch port number where DMA capability is found
68 u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63); in dma_port_match()
70 if (pkg->frame.eof == TB_CFG_PKG_ERROR) in dma_port_match()
72 if (pkg->frame.eof != req->response_type) in dma_port_match()
74 if (route != tb_cfg_get_route(req->request)) in dma_port_match()
76 if (pkg->frame.size != req->response_size) in dma_port_match()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
17 is paired with a custom DMA engine (inventively named "Flash DMA") which
25 -- Additional SoC-specific NAND controller properties --
33 interesting ways, sometimes with registers that lump multiple NAND-related
[all …]
H A Dgpmi-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI)
10 - Han Xu <han.xu@nxp.com>
14 flash chips. The device tree may optionally contain sub-nodes
21 - enum:
22 - fsl,imx23-gpmi-nand
23 - fsl,imx28-gpmi-nand
[all …]
/openbmc/u-boot/board/freescale/m547xevb/
H A DREADME4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init
13 - board/freescale/m547xevb/mii.c MII init
14 - board/freescale/m547xevb/Makefile Makefile
15 - board/freescale/m547xevb/config.mk config make
16 - board/freescale/m547xevb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
20 - arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dxpedite5200.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dmpc8349emitx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC8349E-mITX Device Tree Source
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <32768>;
[all …]
H A Dxpedite5200_xmon.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 * xMon boot loader memory map which differs from U-Boot's.
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 form-factor = "PMC/XMC";
18 boot-bank = <0x0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
39 d-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dtqm8560.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
[all …]
H A Dtqm8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dtqm8548-bigflash.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j7200-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j7200.dtsi"
18 reserved_memory: reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
26 no-map;
29 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
30 compatible = "shared-dma-pool";
[all …]
H A Dk3-j721e-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
20 reserved_memory: reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
28 no-map;
31 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
32 compatible = "shared-dma-pool";
[all …]
/openbmc/linux/drivers/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
16 eeprom and flash memory, codecs and various other controller
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
86 This enables master mode support for the SPIFC (SPI flash
112 tristate "Aspeed flash controllers in SPI mode"
118 to SPI NOR chips, and support for the SPI flash memory
145 supports spi-mem interface.
[all …]
/openbmc/u-boot/arch/sandbox/dts/
H A Dtest.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
27 testfdt6 = "/e-test";
28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Drockchip-sfc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Serial Flash Controller (SFC)
10 - Heiko Stuebner <heiko@sntech.de>
11 - Chris Morgan <macromorgan@hotmail.com>
14 - $ref: spi-controller.yaml#
32 - description: Bus Clock
33 - description: Module Clock
[all …]
H A Damlogic,meson6-spifc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SPI Flash Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 - $ref: spi-controller.yaml#
18 NOR memories, without DMA support and a 64-byte unified transmit /
24 - amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs
25 - amlogic,meson-gxbb-spifc # SPI Flash Controller on GXBB and compatible SoCs
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dintel,ixp4xx-expansion-bus-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
15 - Linus Walleij <linus.walleij@linaro.org>
19 pattern: '^bus@[0-9a-f]+$'
23 - enum:
24 - intel,ixp42x-expansion-bus-controller
25 - intel,ixp43x-expansion-bus-controller
[all …]
/openbmc/qemu/hw/ssi/
H A Daspeed_smc.c2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
26 #include "hw/block/flash.h"
31 #include "qemu/error-report.h"
37 #include "hw/qdev-properties.h"
80 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
82 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
115 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
137 /* DMA DRAM Side Address High Part (AST2700) */
140 /* DMA Control/Status Register */
153 /* DMA Flash Side Address */
[all …]

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