| /openbmc/sdeventplus/src/sdeventplus/source/ |
| H A D | time.hpp | 3 #include <systemd/sd-event.h>
6 #include <sdeventplus/clock.hpp>
31 /** @brief Type used as the basis for absolute clock times */
32 using TimePoint = typename Clock<Id>::time_point;
33 /** @brief Type used to define the accuracy of the time source */
34 using Accuracy = SdEventDuration; typedef in sdeventplus::source::Time
42 * @param[in] event - The event to attach the handler
43 * @param[in] time - Absolute time when the callback should be executed
44 * @param[in] accuracy - Optional amount of error tolerable in time source
45 * @param[in] callback - The function executed on event dispatch
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| H A D | time.cpp | 1 #include <sdeventplus/clock.hpp>
17 Time<Id>::Time(const Event& event, TimePoint time, Accuracy accuracy, in Time() argument
19 Base(event, create_source(event, time, accuracy), std::false_type()) in Time()
42 event.getSdEvent()->sd_event_source_get_time(get(), &usec)); in get_time()
51 event.getSdEvent()->sd_event_source_set_time( in set_time()
56 typename Time<Id>::Accuracy Time<Id>::get_accuracy() const in get_accuracy()
61 event.getSdEvent()->sd_event_source_get_time_accuracy(get(), &usec)); in get_accuracy()
66 void Time<Id>::set_accuracy(Accuracy accuracy) const in set_accuracy()
69 event.getSdEvent()->sd_event_source_set_time_accuracy( in set_accuracy()
70 get(), SdEventDuration(accuracy).count())); in set_accuracy()
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | fixed-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
15 const: fixed-clock
17 "#clock-cells":
20 clock-frequency: true
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-fixed-rate.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Fixed rate clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic fixed-rate clock that cannot gate
20 * Traits of this clock:
21 * prepare - clk_(un)prepare only ensures parents are prepared
22 * enable - clk_enable only ensures parents are enabled
23 * rate - rate is always a fixed value. No clk_set_rate support
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| H A D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
85 unsigned long accuracy; member
116 if (!core->rpm_enabled) in clk_pm_runtime_get()
119 return pm_runtime_resume_and_get(core->dev); in clk_pm_runtime_get()
124 if (!core->rpm_enabled) in clk_pm_runtime_put()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | zynqmp-clk.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Clock specification for Xilinx ZynqMP
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <100000000>;
15 u-boot,dm-pre-reloc;
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <125000000>;
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| /openbmc/linux/Documentation/timers/ |
| H A D | timekeeping.rst | 2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
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| /openbmc/sdeventplus/src/sdeventplus/utility/ |
| H A D | timer.cpp | 1 #include <sdeventplus/clock.hpp>
17 typename source::Time<Id>::Accuracy accuracy) : in Timer() argument
20 Clock<Id>(event).now() + interval.value_or(Duration::zero()), in Timer()
21 accuracy, nullptr) in Timer()
26 timerData->userdata = timerData.get(); in Timer()
29 timerData->internalCallback(); in Timer()
44 userdata->callback = std::move(callback); in set_callback()
68 return userdata->expired; in hasExpired()
80 return userdata->interval; in getInterval()
92 auto now = userdata->clock.now(); in getRemaining()
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| H A D | timer.hpp | 4 #include <sdeventplus/clock.hpp>
41 using Duration = typename Clock<Id>::duration;
51 * @param[in] event - The event we are attaching to
52 * @param[in] callback - The user provided callback run when elapsing
54 * @param[in] interval - Optional amount of time in-between timer
57 * @param[in] accuracy - Optional amount of error tolerable in timer
63 typename source::Time<Id>::Accuracy accuracy =
66 /** @brief Constructs a new non-owning Timer from an existing timer
72 * @param[in] other - The other Timer to copy
73 * @param[in] - Denotes no reference taken or release
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | pc87360.rst | 22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
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| H A D | shtc1.rst | 41 -----------
48 address 0x70. See Documentation/i2c/instantiating-devices.rst for methods to
53 1. blocking (pull the I2C clock line down while performing the measurement) or
54 non-blocking mode. Blocking mode will guarantee the fastest result but
55 the I2C bus will be busy during that time. By default, non-blocking mode
56 is used. Make sure clock-stretching works properly on your device if you
58 2. high or low accuracy. High accuracy is used by default and using it is
61 sysfs-Interface
62 ---------------
65 - temperature input
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| /openbmc/linux/include/linux/ |
| H A D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
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| /openbmc/u-boot/drivers/clk/at91/ |
| H A D | Kconfig | 2 bool "AT91 clock drivers"
6 This option is used to enable the AT91 clock driver.
7 The driver supports the AT91 clock generator, including
8 the oscillators and PLLs, such as main clock, slow clock,
9 PLLA, UTMI PLL. Clocks can also be a source clock of other
10 clocks a tree structure, such as master clock, usb device
11 clock, matrix clock and generic clock.
12 Devices can use a common clock API to request a particular
13 clock, enable it and get its rate.
16 bool "Support UTMI PLL Clock"
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| /openbmc/linux/arch/arm/boot/dts/alphascale/ |
| H A D | alphascale-asm9260.dtsi | 2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
7 #include <dt-bindings/clock/alphascale,asm9260.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&icoll>;
20 #address-cells = <0>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
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| /openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/chrony/ |
| H A D | chrony_4.5.bb | 2 DESCRIPTION = "Chrony can synchronize the system clock with NTP \
14 Typical accuracy between two machines on a LAN is in tens, or a few \
15 hundreds, of microseconds; over the Internet, accuracy is typically \
16 within a few milliseconds. With a good hardware reference clock \
17 sub-microsecond accuracy is possible. \
20 started at boot time and chronyc is a command-line interface program \
30 LICENSE = "GPL-2.0-only"
33 SRC_URI = "https://download.tuxfamily.org/chrony/chrony-${PV}.tar.gz \
39 SRC_URI:append:libc-musl = " \
40 file://0001-Fix-compilation-with-musl.patch \
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| /openbmc/sdeventplus/src/sdeventplus/internal/ |
| H A D | sdevent.cpp | 1 #include <systemd/sd-event.h>
38 sd_event* event, sd_event_source** source, clockid_t clock, uint64_t usec, in sd_event_add_time() argument
39 uint64_t accuracy, sd_event_time_handler_t callback, void* userdata) const in sd_event_add_time() argument
41 return ::sd_event_add_time(event, source, clock, usec, accuracy, callback, in sd_event_add_time()
96 int SdEventImpl::sd_event_now(sd_event* event, clockid_t clock, in sd_event_now() argument
99 return ::sd_event_now(event, clock, usec); in sd_event_now()
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| H A D | sdevent.hpp | 3 #include <systemd/sd-event.h>
27 sd_event* event, sd_event_source** source, clockid_t clock,
28 uint64_t usec, uint64_t accuracy, sd_event_time_handler_t callback,
53 virtual int sd_event_now(sd_event* event, clockid_t clock,
130 clockid_t clock, uint64_t usec, uint64_t accuracy,
166 int sd_event_now(sd_event* event, clockid_t clock,
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| /openbmc/linux/Documentation/sound/designs/ |
| H A D | timestamping.rst | 7 - Trigger_tstamp is the system time snapshot taken when the .trigger
11 estimate with a delay. In the latter two cases, the low-level driver
17 - tstamp is the current system timestamp updated during the last
19 The difference (tstamp - trigger_tstamp) defines the elapsed time.
29 - ``avail`` reports how much can be written in the ring buffer
30 - ``delay`` reports the time it will take to hear a new sample after all
43 ascii-art, this could be represented as follows (for the playback
47 --------------------------------------------------------------> time
53 |< codec delay >|<--hw delay-->|<queued samples>|<---avail->|
54 |<----------------- delay---------------------->| |
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| /openbmc/openbmc/meta-ibm/recipes-support/chrony/chrony/huygens/ |
| H A D | chrony.conf | 7 # Sync to pulse-per-second from an onboard GPS.
12 # compatible = "pps-gpio";
20 # In first three updates step the system clock instead of slew
24 # Record the rate at which the system clock gains/loses time,
25 # improving accuracy after reboot
40 # the server’s clock.
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| /openbmc/linux/arch/arm/boot/dts/intel/pxa/ |
| H A D | pxa300-raumfeld-tuneable-clock.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/maxim,max9485.h>
6 xo_27mhz: oscillator-27mhz {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <27000000>;
10 clock-accuracy = <100>;
14 compatible = "simple-audio-card";
15 simple-audio-card,name = "Raumfeld Speaker";
16 #address-cells = <1>;
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| /openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/chrony/chrony/ |
| H A D | chrony.conf | 14 # Sync to pulse-per-second from an onboard GPS.
19 # compatible = "pps-gpio";
27 # In first three updates step the system clock instead of slew
31 # Record the rate at which the system clock gains/loses time,
32 # improving accuracy after reboot
35 # Enable kernel synchronization of the hardware real-time clock (RTC).
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| /openbmc/u-boot/drivers/rtc/ |
| H A D | Kconfig | 5 menu "Real Time Clock"
11 Enable drver model for real-time-clock drivers. The RTC uclass
20 Enable drver model for real-time-clock drivers. The RTC uclass
29 Enable drver model for real-time-clock drivers. The RTC uclass
38 The PCF2127 is a CMOS Real Time Clock (RTC) and calendar with an integrated
40 crystal optimized for very high accuracy and very low power consumption. The PCF2127
41 has a selectable I2C-bus or SPI-bus, a backup battery switch-over circuit, a
49 compatible Real Time Clock devices.
55 The Renesas (formerly Intersil) ISL1208 is a I2C Real Time Clock (RTC) and
56 calendar with automatic leap year correction, 2-byte battery backed SRAM,
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| /openbmc/linux/arch/x86/kernel/ |
| H A D | tsc_msr.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <asm/intel-family.h>
23 * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
26 * unclear if the root PLL outputs are used directly by the CPU clock PLL or
30 * So we can create a simplified model of the CPU clock setup using a reference
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
62 * Penwell and Clovertrail use spread spectrum clock,
161 * MSR-based CPU/TSC frequency discovery for certain CPUs.
179 freq_desc = (struct freq_desc *)id->driver_data; in cpu_khz_from_msr()
180 if (freq_desc->use_msr_plat) { in cpu_khz_from_msr()
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| /openbmc/linux/drivers/video/fbdev/kyro/ |
| H A D | STG4000InitDevice.c | 41 /* Core clock freq */
44 /* Reference Clock freq */
61 /* PLL Clock */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
133 /* Work out acceptable clock in ProgramClock()
134 * The method calculates ~ +- 0.4% (1/256) in ProgramClock()
136 ulMinClock = coreClock - (coreClock >> 8); in ProgramClock()
139 /* Scale clock required for use in calculations */ in ProgramClock()
147 /* loop for pre-divider from min to max */ in ProgramClock()
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| /openbmc/linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | renesas,rzg2l-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
16 stored in a 32-bit data register corresponding to each channel.
21 - enum:
22 - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
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