| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
11 provides connectivity to an external ethernet PHY supporting different
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
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| H A D | snps,dwc-qos-ethernet.txt | 1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
6 This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
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| H A D | starfive,jh7110-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7110-dwmac
21 - compatible
26 - enum:
27 - starfive,jh7110-dwmac
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| H A D | mediatek-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
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| H A D | intel,dwmac-plat.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
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| H A D | engleder,tsnep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TSN endpoint Ethernet MAC
10 - Gerhard Engleder <gerhard@engleder-embedded.com>
13 - $ref: ethernet-controller.yaml#
20 maxItems: 1
23 minItems: 1
26 interrupt-names:
27 minItems: 1
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| H A D | renesas,etheravb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet AVB
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
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| /openbmc/linux/drivers/net/ethernet/xilinx/ |
| H A D | xilinx_axienet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for Xilinx Axi Ethernet device driver.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
19 #define XAE_HDR_SIZE 14 /* Size of Ethernet header */
20 #define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */
21 #define XAE_MTU 1500 /* Max MTU of an Ethernet frame */
31 #define XAE_OPTION_PROMISC (1 << 0)
34 #define XAE_OPTION_JUMBO (1 << 1)
37 #define XAE_OPTION_VLAN (1 << 2)
40 #define XAE_OPTION_FLOW_CONTROL (1 << 4)
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| H A D | xilinx_axienet_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx Axi Ethernet device driver
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
9 * Copyright (c) 2010 - 2011 PetaLogix
10 * Copyright (c) 2019 - 2022 Calian Advanced Technologies
11 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
13 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
17 * - Add Axi Fifo support.
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| /openbmc/u-boot/doc/device-tree-bindings/net/ |
| H A D | snps,dwc-qos-ethernet.txt | 1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
3 This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
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| H A D | stmmac.txt | 1 * STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
4 - compatible: Should be "snps,dwmac-<ip_version>" "snps,dwmac"
5 For backwards compatibility: "st,spear600-gmac" is also supported.
6 - reg: Address and length of the register set for the device
7 - interrupt-parent: Should be the phandle for the interrupt controller
9 - interrupts: Should contain the STMMAC interrupts
10 - interrupt-names: Should contain the interrupt names "macirq"
13 - phy-mode: See ethernet.txt file in the same directory.
14 - snps,reset-gpio gpio number for phy reset.
15 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | brcm,bus-axi.txt | 1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
29 #size-cells = <1>;
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| /openbmc/qemu/pc-bios/ |
| H A D | petalogix-ml605.dts | 5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = < 0x01 >;
12 #size-cells = < 0x01 >;
22 ethernet0 = "/axi/axi-ethernet@82780000";
23 serial0 = "/axi/serial@83e00000";
28 stdout-path = "/axi/serial@83e00000";
32 #address-cells = < 0x01 >;
34 #size-cells = < 0x00 >;
37 clock-frequency = < 0xbebc200 >;
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| /openbmc/linux/Documentation/networking/device_drivers/ethernet/stmicro/ |
| H A D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Driver for the Synopsys(R) Ethernet Controllers "stmmac"
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
24 This file describes the stmmac Linux Driver for all the Synopsys(R) Ethernet
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
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| H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
21 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
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| /openbmc/linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | dwmac-dwc-qos-eth.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Synopsys DWC Ethernet Quality-of-Service v4.10a linux driver
9 #include <linux/clk-provider.h>
43 struct device *dev = &pdev->dev; in dwc_eth_dwmac_config_dt()
48 if (!plat_dat->axi) { in dwc_eth_dwmac_config_dt()
49 plat_dat->axi = kzalloc(sizeof(struct stmmac_axi), GFP_KERNEL); in dwc_eth_dwmac_config_dt()
51 if (!plat_dat->axi) in dwc_eth_dwmac_config_dt()
52 return -ENOMEM; in dwc_eth_dwmac_config_dt()
55 plat_dat->axi->axi_lpi_en = device_property_read_bool(dev, in dwc_eth_dwmac_config_dt()
56 "snps,en-lpi"); in dwc_eth_dwmac_config_dt()
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| H A D | dwmac1000_dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
19 static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) in dwmac1000_dma_axi() argument
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
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| H A D | stmmac_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2007-2011 STMicroelectronics Ltd
26 * dwmac1000_validate_mcast_bins - validates the number of Multicast filter bins
57 * dwmac1000_validate_ucast_entries - validate the Unicast address entries
63 * supports 1..32, 64, or 128 Unicast filter entries for it's Unicast filter
65 * selected, and defaults to 1 Unicast address if an unsupported
74 case 1 ... 32: in dwmac1000_validate_ucast_entries()
79 x = 1; in dwmac1000_validate_ucast_entries()
88 * stmmac_axi_setup - parse DT parameters for programming the AXI register
91 * if required, from device-tree the AXI internal register can be tuned
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| H A D | stmmac_pci.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2011-2012 Vayavya Labs Pvt Ltd
12 #include <linux/clk-provider.h>
24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
25 plat->has_gmac = 1; in common_default_data()
26 plat->force_sf_dma_mode = 1; in common_default_data()
28 plat->mdio_bus_data->needs_reset = true; in common_default_data()
31 plat->multicast_filter_bins = HASH_TABLE_SIZE; in common_default_data()
34 plat->unicast_filter_entries = 1; in common_default_data()
37 plat->maxmtu = JUMBO_LEN; in common_default_data()
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| /openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| H A D | clk-eth.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/kona-common/clk.h>
11 #include "clk-core.h"
40 /* Enable appropriate clocks for Ethernet */
43 int rc = -1; in clk_eth_enable()
48 writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR); in clk_eth_enable()
59 rc = -1; in clk_eth_enable()
69 if (rc == -1) { in clk_eth_enable()
70 printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n", in clk_eth_enable()
72 return -1; in clk_eth_enable()
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| /openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| H A D | clk-eth.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/kona-common/clk.h>
11 #include "clk-core.h"
40 /* Enable appropriate clocks for Ethernet */
43 int rc = -1; in clk_eth_enable()
48 writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR); in clk_eth_enable()
59 rc = -1; in clk_eth_enable()
69 if (rc == -1) { in clk_eth_enable()
70 printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n", in clk_eth_enable()
72 return -1; in clk_eth_enable()
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| /openbmc/linux/arch/arm/boot/dts/broadcom/ |
| H A D | bcm53573.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
21 stdout-path = "serial0:115200n8";
25 #address-cells = <1>;
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| /openbmc/u-boot/arch/mips/dts/ |
| H A D | nexys4ddr.dts | 1 /dts-v1/;
13 cpuintc: interrupt-controller@0 {
14 #address-cells = <0>;
15 #interrupt-cells = <1>;
16 interrupt-controller;
17 compatible = "mti,cpu-interrupt-controller";
24 axi_ethernetlite: ethernet@10e00000 {
25 compatible = "xlnx,xps-ethernetlite-1.00.a";
27 local-mac-address = [08 86 4C 0D F7 09];
28 phy-handle = <&phy0>;
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| /openbmc/linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-cp11x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
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