bindings/net/xlnx%2Caxi-ethernet.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10   Also called  AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
11   provides connectivity to an external ethernet PHY supporting different
16   Management configuration is done through the AXI interface, while payload is
17   sent and received through means of an AXI DMA controller. This driver
18   includes the DMA driver code, so this driver is incompatible with AXI DMA
22   - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27       - xlnx,axi-ethernet-1.00.a
28       - xlnx,axi-ethernet-1.01.a
29       - xlnx,axi-ethernet-2.01.a
34       and length of the AXI DMA controller IO space, unless
35       axistream-connected is specified, in which case the reg
37     minItems: 1
42       - description: Ethernet core interrupt
43       - description: Tx DMA interrupt
44       - description: Rx DMA interrupt
46       Ethernet core interrupt is optional. If axistream-connected property is
48       resources are mentioned on ethernet node.
49     minItems: 1
51   phy-handle: true
58   phy-mode:
60       - mii
61       - gmii
62       - rgmii
63       - sgmii
64       - 1000base-x
66   xlnx,phy-type:
68       Do not use, but still accepted in preference to phy-mode.
75       1 to enable partial TX checksum offload and 2 to enable full TX
78     enum: [0, 1, 2]
83       1 to enable partial RX checksum offload and 2 to enable full RX
86     enum: [0, 1, 2]
88   xlnx,switch-x-sgmii:
91       Indicate the Ethernet core is configured to support both 1000BaseX and
92       SGMII modes. If set, the phy-mode should be set to match the mode
97       - description: Clock for AXI register slave interface.
98       - description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces.
99       - description: Ethernet reference clock, used by signal delay primitives
101       - description: MGT reference clock (used by optional internal PCS/PMA PHY)
103   clock-names:
105       - const: s_axi_lite_clk
106       - const: axis_clk
107       - const: ref_clk
108       - const: mgt_clk
110   axistream-connected:
112     description: Phandle of AXI DMA controller which contains the resources
113       used by this device. If this is specified, the DMA-related resources
120   pcs-handle:
121     description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
122       modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
123       and "phy-handle" should point to an external PHY if exists.
124     maxItems: 1
127   - compatible
128   - interrupts
129   - reg
130   - xlnx,rxmem
131   - phy-handle
134   - $ref: /schemas/net/ethernet-controller.yaml#
139   - |
140     axi_ethernet_eth: ethernet@40c00000 {
141         compatible = "xlnx,axi-ethernet-1.00.a";
142         interrupts = <2 0 1>;
143         clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
145         phy-mode = "mii";
150         phy-handle = <&phy0>;
153             #address-cells = <1>;
154             #size-cells = <0>;
155             phy0: ethernet-phy@1 {
156                 device_type = "ethernet-phy";
157                 reg = <1>;
162   - |
163     axi_ethernet_eth1: ethernet@40000000 {
164         compatible = "xlnx,axi-ethernet-1.00.a";
166         clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
168         phy-mode = "mii";
173         phy-handle = <&phy1>;
174         axistream-connected = <&dma>;
177             #address-cells = <1>;
178             #size-cells = <0>;
179             phy1: ethernet-phy@1 {
180                 device_type = "ethernet-phy";
181                 reg = <1>;