Searched full:mx6sl (Results 1 – 24 of 24) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | Kconfig | 42 config MX6SL config
314 select MX6SL
506 select MX6SL
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| H A D | soc.c | 465 * i.MX6SL/SX/UL has same layout. in mmc_get_boot_dev()
571 * not output clock after reset, MX6DL and MX6SL have added 396M pfd in s_init()
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| H A D | ddr.c | 923 * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
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| /openbmc/u-boot/board/freescale/mx6memcal/ |
| H A D | Kconfig | 56 bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
61 on most i.MX6SL designs.
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| H A D | spl.c | 336 * for i.MX6SL, UL, ULL in ccgr_init()
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| /openbmc/linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | imx-ocotp.yaml | 14 i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL,
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| /openbmc/u-boot/drivers/fastboot/ |
| H A D | Kconfig | 28 default 0x82000000 if MX6SX || MX6SL || MX6UL || MX6SLL
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| /openbmc/linux/Documentation/devicetree/bindings/power/ |
| H A D | fsl,imx-gpc.yaml | 80 The following additional DOMAIN_INDEX value is valid for i.MX6SL:
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| /openbmc/u-boot/include/configs/ |
| H A D | mx6sllevk.h | 5 * Configuration settings for the Freescale i.MX6SL EVK board.
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| H A D | mx6slevk.h | 5 * Configuration settings for the Freescale i.MX6SL EVK board.
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx6/ |
| H A D | crm_regs.h | 309 /* LCDIF_PIX_PODF on i.MX6SL */
380 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
534 /*LCD on i.MX6SL */
565 /* For i.MX6SL */
800 /* i.MX6SL */
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| H A D | mx6-ddr.h | 22 #include "mx6sl-ddr.h"
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| H A D | imx-regs.h | 268 /* i.MX6SL/SLL */
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| /openbmc/linux/arch/arm/mach-imx/ |
| H A D | anatop.c | 32 /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
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| /openbmc/linux/drivers/soc/imx/ |
| H A D | soc-imx.c | 87 soc_id = "i.MX6SL"; in imx_soc_device_init()
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6sl-tolino-shine3.dts | 10 * In the Toline Shine 3 ebook reader it is a i.MX6SL
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| H A D | imx6sl-tolino-vision5.dts | 10 * In the Tolino Vision 5 ebook reader it is a i.MX6SL
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| H A D | e60k02.dtsi | 12 * the Tolino Shine 3 (with i.MX6SL)
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| H A D | e70k02.dtsi | 12 * the Tolino Shine 3 (with i.MX6SL)
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| /openbmc/u-boot/include/ |
| H A D | fsl_esdhc.h | 205 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
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| /openbmc/u-boot/arch/arm/include/asm/mach-imx/ |
| H A D | iomux-v3.h | 174 /* i.MX6SL/SLL */
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | sdhci-esdhc-imx.c | 106 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
509 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ in esdhc_readl_le()
1446 * TO1.1, it's harmless for MX6SL in sdhci_esdhc_imx_hwinit()
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| /openbmc/linux/arch/arm/ |
| H A D | Kconfig.debug | 484 bool "i.MX6SL Debug UART"
488 on i.MX6SL.
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | fsl.yaml | 581 - description: i.MX6SL based Boards
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