| /openbmc/linux/Documentation/devicetree/bindings/mfd/ |
| H A D | aspeed-lpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Aspeed Low Pin Count (LPC) Bus Controller
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
21 The LPC controller is represented as a multi-function device to account for the
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| /openbmc/phosphor-ipmi-flash/ |
| H A D | meson.options | 5 'bmc-blob-handler',
10 'cleanup-delete',
14 option('host-tool', type: 'feature', description: 'Build the host tool')
18 'host-bios',
24 'reboot-update',
30 'update-status',
37 'update-type',
39 choices: ['none', 'static-layout', 'tarball-ubi'],
44 'lpc-type',
46 choices: ['none', 'aspeed-lpc', 'nuvoton-lpc'],
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| H A D | README.md | 7 [here](https://github.com/openbmc/docs/blob/master/designs/firmware-update-via-blobs.md).
9 ## Building and using the host-tool
11 This repo contains a host-tool implementation for talking to the corresponding
14 ### Building the host-tool
16 The host-tool depends on ipmi-blob-tool and pciutils.
21 [xorg-macros source](https://gitlab.freedesktop.org/xorg/util/macros).
26 ./autogen.sh --prefix=/usr
41 #### Building ipmi-blob-tool
44 [ipmi-blob-tool source](https://github.com/openbmc/ipmi-blob-tool).
62 meson setup -Dexamples=false -Dtests=disabled builddir
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| /openbmc/qemu/include/hw/misc/ |
| H A D | aspeed_scu.h | 9 * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
84 * arch/arm/mach-aspeed/include/mach/regs-scu.h
86 * Copyright (C) 2012-2020 ASPEED Technology Inc.
104 * 22:20 LPC Host LHCLK divider selection
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| /openbmc/u-boot/arch/nds32/include/asm/arch-ag102/ |
| H A D | ag102.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
16 /* LPC Controller */
18 /* LPC Controller */
40 /* AHB Controller */
42 /* AHB-to-APB Bridge Controller */
46 /* Andes Multi-core Interrupt Controller */
54 /* APB - SSP (SPI) (without AC97) Controller */
56 /* UART1 - APB STUART Controller (UART0 in Linux) */
58 /* APB - SSP with HDA/AC97 Controller */
60 /* UART2 - APB STUART Controller (UART1 in Linux) */
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| /openbmc/u-boot/cmd/ |
| H A D | otp_info.h | 7 #define OTP_REG_RESERVED -1
8 #define OTP_REG_VALUE -2
9 #define OTP_REG_VALID_BIT -3
51 { 10, 2, 0, "HCLK ratio AXI:AHB = default" },
52 { 10, 2, 1, "HCLK ratio AXI:AHB = 2:1" },
53 { 10, 2, 2, "HCLK ratio AXI:AHB = 3:1" },
54 { 10, 2, 3, "HCLK ratio AXI:AHB = 4:1" },
74 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
77 { 24, 1, 0, "Enable watchdog to reset full chip" },
78 { 24, 1, 1, "Disable watchdog to reset full chip" },
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-aspeed.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
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| H A D | clk-ast2600.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #define pr_fmt(fmt) "clk-ast2600: " fmt
14 #include <dt-bindings/clock/ast2600-clock.h>
16 #include "clk-aspeed.h"
20 * explicitly-configured clocks (ASPEED_CLK_HPLL and up).
81 * to control the clock enable register and the other to control the reset
82 * IP. This allows us to enforce the ordering:
94 * handled by using -1 as the index for the reset, and the consumer must
99 * ref0 and ref1 are essential for the SoC to operate
104 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
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| /openbmc/linux/drivers/soc/aspeed/ |
| H A D | aspeed-lpc-ctrl.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/aspeed-lpc-ctrl.h>
19 #define DEVICE_NAME "aspeed-lpc-ctrl"
45 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()
52 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()
53 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()
55 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()
56 return -EINVAL; in aspeed_lpc_ctrl_mmap()
58 /* ast2400/2500 AHB accesses are not cache coherent */ in aspeed_lpc_ctrl_mmap()
61 if (remap_pfn_range(vma, vma->vm_start, in aspeed_lpc_ctrl_mmap()
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| /openbmc/phosphor-mboxd/Documentation/ |
| H A D | mbox_protocol.md | 7 http://www.apache.org/licenses/LICENSE-2.0
9 Unless required by applicable law or agreed to in writing, software
17 This document describes a protocol for host to BMC communication via the
19 This protocol is specifically designed to allow a host to request and manage
20 access to a flash device(s) with the specifics of how the host is required to
26 in brackets next to the definition of the functionality. (e.g. (V2) for version
28 implemented by proceeding versions up to and not including the version a command
33 "mbox" is the name we use to represent a protocol we have established between
35 for the host to control access to the flash device(s).
37 Prior to the mbox protocol, the host uses a backdoor into the BMC address space
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| /openbmc/hiomapd/Documentation/ |
| H A D | protocol.md | 7 http://www.apache.org/licenses/LICENSE-2.0
9 Unless required by applicable law or agreed to in writing, software distributed
19 The driving motivation for the protocol is to expose flash devices owned by the
20 BMC to the host. Usually, the flash device of interest is the host's firmware
21 flash device - in some platform designs this is owned by the BMC to enable
22 lights-out updates of the host firmware.
24 As the flash is owned by the BMC, access by the host to its firmware must be
28 2. Conflict of access between the host and the BMC to the flash controller
33 flash data in the LPC firmware space, communicated via functions in the LPC IO
38 The scope of the document is limited to defining the protocol and its
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| /openbmc/qemu/hw/arm/ |
| H A D | aspeed_ast2600.c | 4 * Copyright (c) 2016-2019, IBM Corporation.
7 * the COPYING file in the top-level directory.
15 #include "qemu/error-report.h"
19 #include "target/arm/cpu-qom.h"
28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
96 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
138 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
139 [ASPEED_DEV_PCIE] = 167, /* 167 -> 168 */
146 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
150 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */
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| /openbmc/openbmc/meta-quanta/meta-gbs/recipes-bsp/images/npcm7xx-igps-native/ |
| H A D | BootBlockAndHeader_GBS.xml | 1 <!-- SPDX-License-Identifier: GPL-2.0
6 #--------------------------------------------------------------------------->
8 <?xml version="1.0" encoding="UTF-8"?>
11 <!-- BMC mandatory fields -->
13 <BinSize>0</BinSize> <!-- If 0 the binary size will be calculated by the tool -->
14 <PadValue>0xFF</PadValue> <!-- Byte value to pad the empty areas, default is 0 -->
18 <!-- BootBlock tag (0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42) or
19 uboot tag (0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B) -->
20 <name>StartTag</name> <!-- name of field -->
25 …at='bytes'>0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42</content> <!-- content the user should fill -->
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| /openbmc/u-boot/arch/arm/mach-aspeed/ast2500/ |
| H A D | platform.S | 8 * along with this program; if not, write to the Free Software
9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * [P2] = nice to have
36 * | 2.[P1] Add check code to bypass A0 patch
38 * | 4.[P1] Set X-DMA into VGA memory domain
48 * V7 |2015.09.18 : 1.[P1] Clear AHB bus lock condition at power up time
49 * | 2.[P1] Add reset MMC controller to solve init DRAM again during VGA ON
56 * |2016.01.27 : 1.[P3] Modify the first reset from full chip reset to SOC reset
58 * | 3.[P2] Move the reset_mmc code to be after MPLL initialized
60 * V10|2016.04.21 : 1.[P1] Add USB PHY initial code - port B, to prevent wrong state on USB pins
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| /openbmc/linux/arch/arm/boot/dts/nxp/lpc/ |
| H A D | lpc32xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 #include <dt-bindings/clock/lpc32xx-clock.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&mic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,arm926ej-s";
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| /openbmc/openbmc/meta-yadro/meta-nicole/recipes-bsp/u-boot/files/ |
| H A D | 0003-aspeed-add-gpio-support.patch | 7 to the AHB on the Aspeed 2400/2500.
9 This brings the functions and a shell command to manipulate the GPIO
13 Signed-off-by: Alexander Filippov <a.filippov@yadro.com>
14 ---
15 arch/arm/include/asm/arch-aspeed/gpio.h | 65 ++++
16 arch/arm/include/asm/arch-aspeed/platform.h | 1 +
20 create mode 100644 arch/arm/include/asm/arch-aspeed/gpio.h
23 diff --git a/arch/arm/include/asm/arch-aspeed/gpio.h b/arch/arm/include/asm/arch-aspeed/gpio.h
26 --- /dev/null
27 +++ b/arch/arm/include/asm/arch-aspeed/gpio.h
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| /openbmc/u-boot/arch/arm/mach-aspeed/ast2400/ |
| H A D | platform.S | 8 * along with this program; if not, write to the Free Software
9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * EC1. Modify DQIDLY and DQSI-MCLK2X calibration algorithm
28 * EC6. Remove AST2300-A0 PCI-e workaround
30 * EC8. Remove #define CONFIG_DRAM_UART_OUT, default has message output to UART5
31 * EC9. Add DRAM size auto-detection
33 * EC11. Move the "Solve ASPM" code position of AST2300 to avoid watchdog reset
36 * EC1. Add solution of LPC lock issue due to watchdog reset. (AP note A2300-11)
41 * 1. Change init value of MCR18[4] from '1' to '0'
42 * 2. Add CBR4 code to finetune MCR18[4]
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|
| /openbmc/ |
| D | opengrok1.0.log | 1 2025-03-19 03:00:43.644-0500 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-03-19 03:00:43.767-0500 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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| D | opengrok2.0.log | 1 2025-03-18 03:00:46.767-0500 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-03-18 03:00:46.892-0500 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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| /openbmc/linux/ |
| H A D | opengrok1.0.log | 1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-2
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| H A D | opengrok0.0.log | 1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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| H A D | opengrok2.0.log | 1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-2
[all...] |