1a2db23c1SChia-Wei Wang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2a2db23c1SChia-Wei Wang# # Copyright (c) 2021 Aspeed Tehchnology Inc. 3a2db23c1SChia-Wei Wang%YAML 1.2 4a2db23c1SChia-Wei Wang--- 5a2db23c1SChia-Wei Wang$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# 6a2db23c1SChia-Wei Wang$schema: http://devicetree.org/meta-schemas/core.yaml# 7a2db23c1SChia-Wei Wang 8a2db23c1SChia-Wei Wangtitle: Aspeed Low Pin Count (LPC) Bus Controller 9a2db23c1SChia-Wei Wang 10a2db23c1SChia-Wei Wangmaintainers: 11a2db23c1SChia-Wei Wang - Andrew Jeffery <andrew@aj.id.au> 12a2db23c1SChia-Wei Wang - Chia-Wei Wang <chiawei_wang@aspeedtech.com> 13a2db23c1SChia-Wei Wang 14a2db23c1SChia-Wei Wangdescription: 15a2db23c1SChia-Wei Wang The LPC bus is a means to bridge a host CPU to a number of low-bandwidth 16a2db23c1SChia-Wei Wang peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The 17a2db23c1SChia-Wei Wang primary use case of the Aspeed LPC controller is as a slave on the bus 18a2db23c1SChia-Wei Wang (typically in a Baseboard Management Controller SoC), but under certain 19a2db23c1SChia-Wei Wang conditions it can also take the role of bus master. 20a2db23c1SChia-Wei Wang 21a2db23c1SChia-Wei Wang The LPC controller is represented as a multi-function device to account for the 22a2db23c1SChia-Wei Wang mix of functionality, which includes, but is not limited to 23a2db23c1SChia-Wei Wang 24a2db23c1SChia-Wei Wang * An IPMI Block Transfer[2] Controller 25a2db23c1SChia-Wei Wang 26a2db23c1SChia-Wei Wang * An LPC Host Interface Controller manages functions exposed to the host such 27a2db23c1SChia-Wei Wang as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART 28a2db23c1SChia-Wei Wang management and bus snoop configuration. 29a2db23c1SChia-Wei Wang 30*47aab533SBjorn Helgaas * A set of SuperIO[3] scratch registers enabling implementation of e.g. custom 31a2db23c1SChia-Wei Wang hardware management protocols for handover between the host and baseboard 32a2db23c1SChia-Wei Wang management controller. 33a2db23c1SChia-Wei Wang 34a2db23c1SChia-Wei Wang Additionally the state of the LPC controller influences the pinmux 35a2db23c1SChia-Wei Wang configuration, therefore the host portion of the controller is exposed as a 36a2db23c1SChia-Wei Wang syscon as a means to arbitrate access. 37a2db23c1SChia-Wei Wang 38a2db23c1SChia-Wei Wangproperties: 39a2db23c1SChia-Wei Wang compatible: 40a2db23c1SChia-Wei Wang items: 41a2db23c1SChia-Wei Wang - enum: 42a2db23c1SChia-Wei Wang - aspeed,ast2400-lpc-v2 43a2db23c1SChia-Wei Wang - aspeed,ast2500-lpc-v2 44a2db23c1SChia-Wei Wang - aspeed,ast2600-lpc-v2 45a2db23c1SChia-Wei Wang - const: simple-mfd 46a2db23c1SChia-Wei Wang - const: syscon 47a2db23c1SChia-Wei Wang 48a2db23c1SChia-Wei Wang reg: 49a2db23c1SChia-Wei Wang maxItems: 1 50a2db23c1SChia-Wei Wang 51a2db23c1SChia-Wei Wang "#address-cells": 52a2db23c1SChia-Wei Wang const: 1 53a2db23c1SChia-Wei Wang 54a2db23c1SChia-Wei Wang "#size-cells": 55a2db23c1SChia-Wei Wang const: 1 56a2db23c1SChia-Wei Wang 57a2db23c1SChia-Wei Wang ranges: true 58a2db23c1SChia-Wei Wang 59a2db23c1SChia-Wei WangpatternProperties: 60a2db23c1SChia-Wei Wang "^lpc-ctrl@[0-9a-f]+$": 61a2db23c1SChia-Wei Wang type: object 62a2db23c1SChia-Wei Wang additionalProperties: false 63a2db23c1SChia-Wei Wang 64a2db23c1SChia-Wei Wang description: | 65a2db23c1SChia-Wei Wang The LPC Host Interface Controller manages functions exposed to the host such as 66a2db23c1SChia-Wei Wang LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management 67a2db23c1SChia-Wei Wang and bus snoop configuration. 68a2db23c1SChia-Wei Wang 69a2db23c1SChia-Wei Wang properties: 70a2db23c1SChia-Wei Wang compatible: 71a2db23c1SChia-Wei Wang items: 72a2db23c1SChia-Wei Wang - enum: 73a2db23c1SChia-Wei Wang - aspeed,ast2400-lpc-ctrl 74a2db23c1SChia-Wei Wang - aspeed,ast2500-lpc-ctrl 75a2db23c1SChia-Wei Wang - aspeed,ast2600-lpc-ctrl 76a2db23c1SChia-Wei Wang 77a2db23c1SChia-Wei Wang reg: 78a2db23c1SChia-Wei Wang maxItems: 1 79a2db23c1SChia-Wei Wang 80a2db23c1SChia-Wei Wang clocks: 81a2db23c1SChia-Wei Wang maxItems: 1 82a2db23c1SChia-Wei Wang 83a2db23c1SChia-Wei Wang memory-region: 84a2db23c1SChia-Wei Wang maxItems: 1 85a2db23c1SChia-Wei Wang description: handle to memory reservation for the LPC to AHB mapping region 86a2db23c1SChia-Wei Wang 87a2db23c1SChia-Wei Wang flash: 88a2db23c1SChia-Wei Wang $ref: /schemas/types.yaml#/definitions/phandle 89a2db23c1SChia-Wei Wang description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping 90a2db23c1SChia-Wei Wang 91a2db23c1SChia-Wei Wang required: 92a2db23c1SChia-Wei Wang - compatible 93a2db23c1SChia-Wei Wang - clocks 94a2db23c1SChia-Wei Wang 95a2db23c1SChia-Wei Wang "^reset-controller@[0-9a-f]+$": 96a2db23c1SChia-Wei Wang type: object 97a2db23c1SChia-Wei Wang additionalProperties: false 98a2db23c1SChia-Wei Wang 99a2db23c1SChia-Wei Wang description: 100a2db23c1SChia-Wei Wang The UARTs present in the ASPEED SoC can have their resets tied to the reset 101a2db23c1SChia-Wei Wang state of the LPC bus. Some systems may chose to modify this configuration 102a2db23c1SChia-Wei Wang 103a2db23c1SChia-Wei Wang properties: 104a2db23c1SChia-Wei Wang compatible: 105a2db23c1SChia-Wei Wang items: 106a2db23c1SChia-Wei Wang - enum: 107a2db23c1SChia-Wei Wang - aspeed,ast2400-lpc-reset 108a2db23c1SChia-Wei Wang - aspeed,ast2500-lpc-reset 109a2db23c1SChia-Wei Wang - aspeed,ast2600-lpc-reset 110a2db23c1SChia-Wei Wang 111a2db23c1SChia-Wei Wang reg: 112a2db23c1SChia-Wei Wang maxItems: 1 113a2db23c1SChia-Wei Wang 114a2db23c1SChia-Wei Wang '#reset-cells': 115a2db23c1SChia-Wei Wang const: 1 116a2db23c1SChia-Wei Wang 117a2db23c1SChia-Wei Wang required: 118a2db23c1SChia-Wei Wang - compatible 119a2db23c1SChia-Wei Wang - '#reset-cells' 120a2db23c1SChia-Wei Wang 121a2db23c1SChia-Wei Wang "^lpc-snoop@[0-9a-f]+$": 122a2db23c1SChia-Wei Wang type: object 123a2db23c1SChia-Wei Wang additionalProperties: false 124a2db23c1SChia-Wei Wang 125a2db23c1SChia-Wei Wang description: 126a2db23c1SChia-Wei Wang The LPC snoop interface allows the BMC to listen on and record the data 127a2db23c1SChia-Wei Wang bytes written by the Host to the targeted LPC I/O pots. 128a2db23c1SChia-Wei Wang 129a2db23c1SChia-Wei Wang properties: 130a2db23c1SChia-Wei Wang compatible: 131a2db23c1SChia-Wei Wang items: 132a2db23c1SChia-Wei Wang - enum: 133a2db23c1SChia-Wei Wang - aspeed,ast2400-lpc-snoop 134a2db23c1SChia-Wei Wang - aspeed,ast2500-lpc-snoop 135a2db23c1SChia-Wei Wang - aspeed,ast2600-lpc-snoop 136a2db23c1SChia-Wei Wang 137a2db23c1SChia-Wei Wang reg: 138a2db23c1SChia-Wei Wang maxItems: 1 139a2db23c1SChia-Wei Wang 140a2db23c1SChia-Wei Wang interrupts: 141a2db23c1SChia-Wei Wang maxItems: 1 142a2db23c1SChia-Wei Wang 143a2db23c1SChia-Wei Wang snoop-ports: 144a2db23c1SChia-Wei Wang $ref: /schemas/types.yaml#/definitions/uint32-array 145a2db23c1SChia-Wei Wang description: The LPC I/O ports to snoop 146a2db23c1SChia-Wei Wang 147a2db23c1SChia-Wei Wang required: 148a2db23c1SChia-Wei Wang - compatible 149a2db23c1SChia-Wei Wang - interrupts 150a2db23c1SChia-Wei Wang - snoop-ports 151a2db23c1SChia-Wei Wang 152ae11ad38SChia-Wei Wang "^uart-routing@[0-9a-f]+$": 153ae11ad38SChia-Wei Wang $ref: /schemas/soc/aspeed/uart-routing.yaml# 154ae11ad38SChia-Wei Wang description: The UART routing control under LPC register space 155ae11ad38SChia-Wei Wang 156a2db23c1SChia-Wei Wangrequired: 157a2db23c1SChia-Wei Wang - compatible 158a2db23c1SChia-Wei Wang - reg 159a2db23c1SChia-Wei Wang - "#address-cells" 160a2db23c1SChia-Wei Wang - "#size-cells" 161a2db23c1SChia-Wei Wang - ranges 162a2db23c1SChia-Wei Wang 163a2db23c1SChia-Wei WangadditionalProperties: 164a2db23c1SChia-Wei Wang type: object 165a2db23c1SChia-Wei Wang 166a2db23c1SChia-Wei Wangexamples: 167a2db23c1SChia-Wei Wang - | 168a2db23c1SChia-Wei Wang #include <dt-bindings/interrupt-controller/arm-gic.h> 169a2db23c1SChia-Wei Wang #include <dt-bindings/clock/ast2600-clock.h> 170a2db23c1SChia-Wei Wang 171a2db23c1SChia-Wei Wang lpc: lpc@1e789000 { 172a2db23c1SChia-Wei Wang compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; 173a2db23c1SChia-Wei Wang reg = <0x1e789000 0x1000>; 174a2db23c1SChia-Wei Wang 175a2db23c1SChia-Wei Wang #address-cells = <1>; 176a2db23c1SChia-Wei Wang #size-cells = <1>; 177a2db23c1SChia-Wei Wang ranges = <0x0 0x1e789000 0x1000>; 178a2db23c1SChia-Wei Wang 179a2db23c1SChia-Wei Wang lpc_ctrl: lpc-ctrl@80 { 180a2db23c1SChia-Wei Wang compatible = "aspeed,ast2600-lpc-ctrl"; 181a2db23c1SChia-Wei Wang reg = <0x80 0x80>; 182a2db23c1SChia-Wei Wang clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 183a2db23c1SChia-Wei Wang memory-region = <&flash_memory>; 184a2db23c1SChia-Wei Wang flash = <&spi>; 185a2db23c1SChia-Wei Wang }; 186a2db23c1SChia-Wei Wang 187a2db23c1SChia-Wei Wang lpc_reset: reset-controller@98 { 188a2db23c1SChia-Wei Wang compatible = "aspeed,ast2600-lpc-reset"; 189a2db23c1SChia-Wei Wang reg = <0x98 0x4>; 190a2db23c1SChia-Wei Wang #reset-cells = <1>; 191a2db23c1SChia-Wei Wang }; 192a2db23c1SChia-Wei Wang 193a2db23c1SChia-Wei Wang lpc_snoop: lpc-snoop@90 { 194a2db23c1SChia-Wei Wang compatible = "aspeed,ast2600-lpc-snoop"; 195a2db23c1SChia-Wei Wang reg = <0x90 0x8>; 196a2db23c1SChia-Wei Wang interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 197a2db23c1SChia-Wei Wang snoop-ports = <0x80>; 198a2db23c1SChia-Wei Wang }; 199a2db23c1SChia-Wei Wang }; 200