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/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos-arm64.c43 * @np: CMU device tree node with "reg" property (CMU addr)
77 * exynos_arm64_enable_bus_clk - Enable parent clock of specified CMU
81 * @np: CMU device tree node
82 * @cmu: CMU data
84 * Keep CMU parent clock running (needed for CMU registers access).
89 struct device_node *np, const struct samsung_cmu_info *cmu) in exynos_arm64_enable_bus_clk() argument
93 if (!cmu->clk_name) in exynos_arm64_enable_bus_clk()
99 parent_clk = clk_get(dev, cmu->clk_name); in exynos_arm64_enable_bus_clk()
104 parent_clk = of_clk_get_by_name(np, cmu->clk_name); in exynos_arm64_enable_bus_clk()
114 const struct samsung_cmu_info *cmu) in exynos_arm64_cmu_prepare_pm() argument
[all …]
H A Dclk.c58 * @dev: CMU device to enable runtime PM, or NULL if RPM is not needed
59 * @base: Start address (mapped) of CMU registers
339 * samsung_cmu_register_clocks() - Register all clocks provided in CMU object
341 * @cmu: CMU object with clocks to register
344 const struct samsung_cmu_info *cmu) in samsung_cmu_register_clocks() argument
346 if (cmu->pll_clks) in samsung_cmu_register_clocks()
347 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks); in samsung_cmu_register_clocks()
348 if (cmu->mux_clks) in samsung_cmu_register_clocks()
349 samsung_clk_register_mux(ctx, cmu->mux_clks, cmu->nr_mux_clks); in samsung_cmu_register_clocks()
350 if (cmu->div_clks) in samsung_cmu_register_clocks()
[all …]
H A Dclk-exynos5-subcmu.c17 static const struct exynos5_subcmu_info **cmu; variable
48 * Pass the needed clock provider context and register sub-CMU clocks
62 cmu = _cmu; in exynos5_subcmus_init()
166 if (strcmp(cmu[i]->pd_name, name) == 0) in exynos5_clk_probe()
168 cmu[i], np); in exynos5_clk_probe()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5433-clock.yaml29 - samsung,exynos5433-cmu-top
31 - samsung,exynos5433-cmu-cpif
33 - samsung,exynos5433-cmu-mif
36 - samsung,exynos5433-cmu-peric
38 - samsung,exynos5433-cmu-peris
40 - samsung,exynos5433-cmu-fsys
41 - samsung,exynos5433-cmu-g2d
43 - samsung,exynos5433-cmu-disp
44 - samsung,exynos5433-cmu-aud
45 - samsung,exynos5433-cmu-bus0
[all …]
H A Dsamsung,exynos850-clock.yaml17 Exynos850 clock controller is comprised of several CMU units, generating
18 clocks for different domains. Those CMU units are modeled as separate device
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
34 - samsung,exynos850-cmu-top
35 - samsung,exynos850-cmu-apm
36 - samsung,exynos850-cmu-aud
37 - samsung,exynos850-cmu-cmgp
38 - samsung,exynos850-cmu-core
39 - samsung,exynos850-cmu-dpu
40 - samsung,exynos850-cmu-g3d
[all …]
H A Dsamsung,exynosautov9-clock.yaml17 Exynos Auto v9 clock controller is comprised of several CMU units, generating
18 clocks for different domains. Those CMU units are modeled as separate device
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
35 - samsung,exynosautov9-cmu-top
36 - samsung,exynosautov9-cmu-busmc
37 - samsung,exynosautov9-cmu-core
38 - samsung,exynosautov9-cmu-fsys0
39 - samsung,exynosautov9-cmu-fsys1
40 - samsung,exynosautov9-cmu-fsys2
41 - samsung,exynosautov9-cmu-peric0
[all …]
H A Dactions,owl-cmu.txt1 * Actions Semi Owl Clock Management Unit (CMU)
10 "actions,s900-cmu"
11 "actions,s700-cmu"
12 "actions,s500-cmu"
23 dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or
24 actions,s500-cmu.h header and can be used in device tree sources.
31 Actions Semi S900 CMU also requires one more clock:
36 cmu: clock-controller@e0160000 {
37 compatible = "actions,s900-cmu";
51 clocks = <&cmu CLK_UART5>;
H A Dsamsung,exynos7885-clock.yaml17 Exynos7885 clock controller is comprised of several CMU units, generating
18 clocks for different domains. Those CMU units are modeled as separate device
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
34 - samsung,exynos7885-cmu-top
35 - samsung,exynos7885-cmu-core
36 - samsung,exynos7885-cmu-fsys
37 - samsung,exynos7885-cmu-peri
58 const: samsung,exynos7885-cmu-top
74 const: samsung,exynos7885-cmu-core
96 const: samsung,exynos7885-cmu-fsys
[all …]
H A Dsamsung,exynos-clock.yaml23 - samsung,exynos3250-cmu
24 - samsung,exynos3250-cmu-dmc
25 - samsung,exynos3250-cmu-isp
H A Dtesla,fsd-clock.yaml15 (CMU), which generates clocks for various inteernal SoC blocks.
24 - tesla,fsd-clock-cmu
51 const: tesla,fsd-clock-cmu
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250.dtsi81 clocks = <&cmu CLK_DIV_ACLK_200>;
89 clocks = <&cmu CLK_DIV_ACLK_266>;
117 clocks = <&cmu CLK_DIV_ACLK_160>;
125 clocks = <&cmu CLK_DIV_GDL>;
133 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
161 clocks = <&cmu CLK_SCLK_MFC>;
169 clocks = <&cmu CLK_DIV_ACLK_100>;
191 clocks = <&cmu CLK_DIV_GDR>;
217 clocks = <&cmu CLK_ARM_CLK>;
240 clocks = <&cmu CLK_ARM_CLK>;
[all …]
H A Dexynos3250-artik5-eval.dts49 assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>,
50 <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>;
51 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */
52 <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */
53 <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */
54 <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */
/openbmc/linux/arch/arm64/boot/dts/actions/
H A Ds900.dtsi6 #include <dt-bindings/clock/actions,s900-cmu.h>
125 clocks = <&cmu CLK_UART0>;
133 clocks = <&cmu CLK_UART1>;
141 clocks = <&cmu CLK_UART2>;
149 clocks = <&cmu CLK_UART3>;
157 clocks = <&cmu CLK_UART4>;
165 clocks = <&cmu CLK_UART5>;
173 clocks = <&cmu CLK_UART6>;
184 cmu: clock-controller@e0160000 { label
185 compatible = "actions,s900-cmu";
[all …]
H A Ds700.dtsi6 #include <dt-bindings/clock/actions,s700-cmu.h>
119 clocks = <&cmu CLK_UART0>;
127 clocks = <&cmu CLK_UART1>;
135 clocks = <&cmu CLK_UART2>;
143 clocks = <&cmu CLK_UART3>;
151 clocks = <&cmu CLK_UART4>;
159 clocks = <&cmu CLK_UART5>;
167 clocks = <&cmu CLK_UART6>;
172 cmu: clock-controller@e0168000 { label
173 compatible = "actions,s700-cmu";
[all …]
/openbmc/linux/arch/arm/boot/dts/actions/
H A Dowl-s500.dtsi8 #include <dt-bindings/clock/actions,s500-cmu.h>
136 clocks = <&cmu CLK_UART0>;
144 clocks = <&cmu CLK_UART1>;
152 clocks = <&cmu CLK_UART2>;
160 clocks = <&cmu CLK_UART3>;
168 clocks = <&cmu CLK_UART4>;
176 clocks = <&cmu CLK_UART5>;
184 clocks = <&cmu CLK_UART6>;
188 cmu: clock-controller@b0160000 { label
189 compatible = "actions,s500-cmu";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dactions,owl-emac.yaml72 #include <dt-bindings/clock/actions,s500-cmu.h>
80 clocks = <&cmu 59 /*CLK_ETHERNET*/>, <&cmu CLK_RMII_REF>;
82 resets = <&cmu RESET_ETHERNET>;
/openbmc/u-boot/drivers/clk/exynos/
H A Dclk-exynos7420.c19 /* CMU TOPC block device structure */
31 /* CMU TOP0 block device structure */
40 * struct exynos7420_clk_topc_priv - private data for CMU topc clock driver.
42 * @topc: base address of the memory mapped CMU TOPC controller.
55 * struct exynos7420_clk_top0_priv - private data for CMU top0 clock driver.
57 * @top0: base address of the memory mapped CMU TOP0 controller.
/openbmc/u-boot/arch/arm/dts/
H A Ds900.dtsi39 clocks = <&cmu CLOCK_UART5>;
43 cmu: clock-controller@e0160000 { label
45 compatible = "actions,s900-cmu";
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos850.dtsi236 compatible = "samsung,exynos850-cmu-peri";
248 compatible = "samsung,exynos850-cmu-g3d";
257 compatible = "samsung,exynos850-cmu-apm";
266 compatible = "samsung,exynos850-cmu-cmgp";
275 compatible = "samsung,exynos850-cmu-core";
289 compatible = "samsung,exynos850-cmu-top";
298 compatible = "samsung,exynos850-cmu-mfcmscl";
313 compatible = "samsung,exynos850-cmu-dpu";
322 compatible = "samsung,exynos850-cmu-hsi";
335 compatible = "samsung,exynos850-cmu-is";
[all …]
H A Dexynos5433.dtsi369 compatible = "samsung,exynos5433-cmu-top";
384 compatible = "samsung,exynos5433-cmu-cpif";
393 compatible = "samsung,exynos5433-cmu-mif";
404 compatible = "samsung,exynos5433-cmu-peric";
410 compatible = "samsung,exynos5433-cmu-peris";
416 compatible = "samsung,exynos5433-cmu-fsys";
443 compatible = "samsung,exynos5433-cmu-g2d";
457 compatible = "samsung,exynos5433-cmu-disp";
483 compatible = "samsung,exynos5433-cmu-aud";
492 compatible = "samsung,exynos5433-cmu-bus0";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dowl-mmc.yaml60 clocks = <&cmu 56>;
61 resets = <&cmu 23>;
/openbmc/openbmc/poky/meta/files/common-licenses/
H A DBSD-Attribution-HPND-disclaimer24 tech-transfer@andrew.cmu.edu
29 at Carnegie Mellon University (http://www.cmu.edu/computing/)."
/openbmc/u-boot/drivers/soc/keystone/
H A Dkeystone_serdes.c44 struct serdes_cfg cmu[SERDES_CMU_CFG_NUM]; member
69 .cmu = {
130 ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM); in ks2_serdes_init_cfg()
146 /* Enable CMU and COMLANE */ in ks2_serdes_cmu_comlane_enable()
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-owl.yaml52 #include <dt-bindings/clock/actions,s900-cmu.h>
58 clocks = <&cmu CLK_I2C0>;
/openbmc/linux/arch/powerpc/platforms/44x/
H A Dfsp2.c32 #define FSP2_CMU_ERR "ibm,cmu-error-irq"
132 pr_err("CMU Error\n"); in cmu_err_handler()
134 panic("CMU Error\n"); in cmu_err_handler()
260 * recorded in the CMU FIR and leading to erroneous interrupt requests in fsp2_probe()
261 * once the CMU interrupt is unmasked. in fsp2_probe()

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