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/openbmc/linux/include/uapi/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
[all …]
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
45 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
46 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
58 /* Media-dependent registers. */
59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
60 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
61 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
62 * Lanes B-D are numbered 134-136. */
[all …]
/openbmc/u-boot/include/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
20 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
21 #define MII_STAT1000 0x0a /* 1000BASE-T status */
27 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
39 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
52 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
55 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
57 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
60 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
[all …]
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
24 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
44 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
45 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
52 /* Media-dependent registers. */
53 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
54 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
55 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
56 * Lanes B-D are numbered 134-136. */
[all …]
/openbmc/qemu/include/hw/net/
H A Dmii.h8 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
34 #define MII_CTRL1000 9 /* 1000BASE-T control */
35 #define MII_STAT1000 10 /* 1000BASE-T status */
56 #define MII_BMCR_SPEED1000 (1 << 6) /* MSB of Speed (1000) */
59 #define MII_BMSR_100TX_FD (1 << 14) /* Can do 100mbps, full-duplex */
60 #define MII_BMSR_100TX_HD (1 << 13) /* Can do 100mbps, half-duplex */
61 #define MII_BMSR_10T_FD (1 << 12) /* Can do 10mbps, full-duplex */
62 #define MII_BMSR_10T_HD (1 << 11) /* Can do 10mbps, half-duplex */
63 #define MII_BMSR_100T2_FD (1 << 10) /* Can do 100mbps T2, full-duplex */
64 #define MII_BMSR_100T2_HD (1 << 9) /* Can do 100mbps T2, half-duplex */
[all …]
/openbmc/u-boot/drivers/usb/eth/
H A DKconfig3 ---help---
12 ---help---
19 ---help---
27 ---help---
28 Say Y here if you would like to support Microchip LAN75XX Hi-Speed
29 USB 2.0 to 10/100/1000 Gigabit Ethernet controller.
30 Supports 10Base-T/ 100Base-TX/1000Base-T.
37 ---help---
39 Gen 1 to 10/100/1000 Gigabit Ethernet controller.
40 Supports 10Base-T/ 100Base-TX/1000Base-T.
[all …]
/openbmc/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
26 #define SPEED_1000 1000
149 /* IRQ Anti-Lost Timer Initial Value Register */
228 /* MAC Half-Duplex Control Register */
246 /* Wake-On-Lan control register */
[all …]
/openbmc/u-boot/common/
H A Dmiiphyutil.c1 // SPDX-License-Identifier: GPL-2.0+
8 * This provides a bit-banged interface to the ethernet MII management
50 if (strcmp(dev->name, devname) == 0) in miiphy_get_dev_by_name()
78 INIT_LIST_HEAD(&bus->link); in mdio_alloc()
90 if (!bus || !bus->read || !bus->write) in mdio_register()
91 return -1; in mdio_register()
94 if (miiphy_get_dev_by_name(bus->name)) { in mdio_register()
96 bus->name); in mdio_register()
97 return -1; in mdio_register()
101 list_add_tail(&bus->link, &mii_devs); in mdio_register()
[all …]
/openbmc/linux/drivers/watchdog/
H A Dmt7621_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Ralink MT7621/MT7628 built-in hardware watchdog timer
35 void __iomem *base; member
47 static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val) in rt_wdt_w32() argument
49 iowrite32(val, base + reg); in rt_wdt_w32()
52 static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg) in rt_wdt_r32() argument
54 return ioread32(base + reg); in rt_wdt_r32()
61 rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART); in mt7621_wdt_ping()
66 static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t) in mt7621_wdt_set_timeout() argument
70 w->timeout = t; in mt7621_wdt_set_timeout()
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/openbmc/qemu/tests/qemu-iotests/
H A D204.out4 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=134217728
7 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 backing_file=TEST_DIR/t.IMGFMT.base backi…
11 == constrained alignment and max-transfer ==
12 wrote 131072/131072 bytes at offset 1000
14 read 131072/131072 bytes at offset 1000
17 == write zero with constrained max-transfer ==
21 == non-power-of-2 write zeroes limits ==
25 == non-power-of-2 discard limits ==
31 16/1000 bytes allocated at offset 110 MiB
37 read 1000/1000 bytes at offset 0
[all …]
H A D177.out4 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=134217728
7 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 backing_file=TEST_DIR/t.IMGFMT.base backi…
11 == constrained alignment and max-transfer ==
12 wrote 131072/131072 bytes at offset 1000
14 read 131072/131072 bytes at offset 1000
17 == write zero with constrained max-transfer ==
21 == non-power-of-2 write zeroes limits ==
25 == non-power-of-2 discard limits ==
30 read 1000/1000 bytes at offset 0
31 1000 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
/openbmc/linux/include/linux/
H A Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/mii.h: definitions for MII-compatible transceivers
53 return (struct mii_ioctl_data *) &rq->ifr_ifru; in if_mii()
66 * between 100T-full and 100T-half. If your phy does not support
90 * @duplex_lock: Non-zero if duplex is locked at full
196 * MII_CTRL1000 register when in 1000T mode.
216 * MII_CTRL1000 register when in 1000T mode.
237 * bits, when in 1000Base-T mode, to ethtool
257 * bits, when in 1000Base-T mode, to ethtool
275 * bits, when in 1000Base-T mode, to ethtool
[all …]
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define MII_GBCR 9 /* 1000Base-T control register */
19 #define MII_GBSR 10 /* 1000Base-T status register */
21 /* 1000Base-T control register fields */
28 /* 1000Base-T status register fields */
/openbmc/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
36 #include <linux/platform_data/mtd-nand-omap2.h>
38 #define DEVICE_NAME "omap-gpmc"
98 * facilitate bug detection; even if we didn't boot from ROM.
257 /* Define chip-selects as reserved by default until probe completes */
298 rate /= 1000; in gpmc_get_fclk_period()
305 * gpmc_get_clk_period - get period of selected clock domain in ps
[all …]
/openbmc/linux/net/ethtool/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
12 [NETIF_F_SG_BIT] = "tx-scatter-gather",
13 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",
14 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",
15 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",
17 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",
18 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",
20 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",
21 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
22 [NETIF_F_HW_VLAN_STAG_TX_BIT] = "tx-vlan-stag-hw-insert",
[all …]
/openbmc/u-boot/arch/nds32/cpu/n1213/ag101/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Po-Yu Chuang <ratbert@faraday-tech.com>
26 writel(0, &tmr->cr); in timer_init()
34 writel(TIMER_LOAD_VAL, &tmr->timer3_load); in timer_init()
35 writel(TIMER_LOAD_VAL, &tmr->timer3_counter); in timer_init()
36 writel(0, &tmr->timer3_match1); in timer_init()
37 writel(0, &tmr->timer3_match2); in timer_init()
39 /* we don't want timer to issue interrupts */ in timer_init()
43 &tmr->interrupt_mask); in timer_init()
45 cr = readl(&tmr->cr); in timer_init()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_utils.h43 #define FDO_BUG_URL "https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs"
70 #define i915_inject_probe_failure(i915) i915_inject_probe_error((i915), -ENODEV)
77 #define add_overflows_t(T, A, B) \ argument
78 __builtin_add_overflow_p((A), (B), (T)0)
80 #define add_overflows_t(T, A, B) ({ \ argument
83 (T)(a + b) < a; \
96 start__ >= max__ || size__ > max__ - start__; \
108 start__ > max__ || size__ > max__ - start__; \
116 (typeof(ptr))(__v & -BIT(n)); \
119 #define ptr_unmask_bits(ptr, n) ((unsigned long)(ptr) & (BIT(n) - 1))
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/openbmc/linux/arch/mips/alchemy/common/
H A Dusb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * area. Au1550 has OHCI on different base address. No need to handle
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
98 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) in __au1300_usb_phyctl() argument
102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgt215.c25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
120 hi--; in gt215_link_train_calc()
125 median[i] = ((hi - lo) >> 1) + lo; in gt215_link_train_calc()
138 train->r_100720 = 0; in gt215_link_train_calc()
143 train->r_100720 |= ((median[i] & 0x0f) << (i << 2)); in gt215_link_train_calc()
146 train->r_1111e0 = 0x02000000 | (bin * 0x101); in gt215_link_train_calc()
147 train->r_111400 = 0x0; in gt215_link_train_calc()
156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train()
[all …]
/openbmc/linux/drivers/gpu/drm/omapdrm/dss/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
35 pll->dss = dss; in dss_pll_register()
40 return -EBUSY; in dss_pll_register()
45 struct dss_device *dss = pll->dss; in dss_pll_unregister()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
[all …]
/openbmc/linux/drivers/leds/
H A Dleds-lm3533.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * leds-lm3533.c -- LM3533 LED driver
5 * Copyright (C) 2011-2012 Texas Instruments
61 return led->id + 2; in lm3533_led_get_ctrlbank_id()
64 static inline u8 lm3533_led_get_lv_reg(struct lm3533_led *led, u8 base) in lm3533_led_get_lv_reg() argument
66 return base + led->id; in lm3533_led_get_lv_reg()
71 return led->id; in lm3533_led_get_pattern()
75 u8 base) in lm3533_led_get_pattern_reg() argument
77 return base + lm3533_led_get_pattern(led) * LM3533_REG_PATTERN_STEP; in lm3533_led_get_pattern_reg()
88 dev_dbg(led->cdev.dev, "%s - %d\n", __func__, enable); in lm3533_led_pattern_enable()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8188-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
28 gpio-ranges:
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
246 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
258 #define SPEED_1000 1000
[all …]
/openbmc/linux/drivers/cpufreq/
H A Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
24 #include "cpufreq-dt.h"
73 #define MIN_VOLT_MV 1000
109 /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
110 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
111 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
112 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
132 static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, in armada37xx_cpufreq_dvfs_setup() argument
166 * Set cpu divider based on the pre-computed array in in armada37xx_cpufreq_dvfs_setup()
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