1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2f7917c00SJeff Kirsher /* $Date: 2005/03/07 23:59:05 $ $RCSfile: mv88e1xxx.h,v $ $Revision: 1.13 $ */ 3f7917c00SJeff Kirsher #ifndef CHELSIO_MV8E1XXX_H 4f7917c00SJeff Kirsher #define CHELSIO_MV8E1XXX_H 5f7917c00SJeff Kirsher 6f7917c00SJeff Kirsher #ifndef BMCR_SPEED1000 7f7917c00SJeff Kirsher # define BMCR_SPEED1000 0x40 8f7917c00SJeff Kirsher #endif 9f7917c00SJeff Kirsher 10f7917c00SJeff Kirsher #ifndef ADVERTISE_PAUSE 11f7917c00SJeff Kirsher # define ADVERTISE_PAUSE 0x400 12f7917c00SJeff Kirsher #endif 13f7917c00SJeff Kirsher #ifndef ADVERTISE_PAUSE_ASYM 14f7917c00SJeff Kirsher # define ADVERTISE_PAUSE_ASYM 0x800 15f7917c00SJeff Kirsher #endif 16f7917c00SJeff Kirsher 17f7917c00SJeff Kirsher /* Gigabit MII registers */ 18f7917c00SJeff Kirsher #define MII_GBCR 9 /* 1000Base-T control register */ 19f7917c00SJeff Kirsher #define MII_GBSR 10 /* 1000Base-T status register */ 20f7917c00SJeff Kirsher 21f7917c00SJeff Kirsher /* 1000Base-T control register fields */ 22f7917c00SJeff Kirsher #define GBCR_ADV_1000HALF 0x100 23f7917c00SJeff Kirsher #define GBCR_ADV_1000FULL 0x200 24f7917c00SJeff Kirsher #define GBCR_PREFER_MASTER 0x400 25f7917c00SJeff Kirsher #define GBCR_MANUAL_AS_MASTER 0x800 26f7917c00SJeff Kirsher #define GBCR_MANUAL_CONFIG_ENABLE 0x1000 27f7917c00SJeff Kirsher 28f7917c00SJeff Kirsher /* 1000Base-T status register fields */ 29f7917c00SJeff Kirsher #define GBSR_LP_1000HALF 0x400 30f7917c00SJeff Kirsher #define GBSR_LP_1000FULL 0x800 31f7917c00SJeff Kirsher #define GBSR_REMOTE_OK 0x1000 32f7917c00SJeff Kirsher #define GBSR_LOCAL_OK 0x2000 33f7917c00SJeff Kirsher #define GBSR_LOCAL_MASTER 0x4000 34f7917c00SJeff Kirsher #define GBSR_MASTER_FAULT 0x8000 35f7917c00SJeff Kirsher 36f7917c00SJeff Kirsher /* Marvell PHY interrupt status bits. */ 37f7917c00SJeff Kirsher #define MV88E1XXX_INTR_JABBER 0x0001 38f7917c00SJeff Kirsher #define MV88E1XXX_INTR_POLARITY_CHNG 0x0002 39f7917c00SJeff Kirsher #define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010 40f7917c00SJeff Kirsher #define MV88E1XXX_INTR_DOWNSHIFT 0x0020 41f7917c00SJeff Kirsher #define MV88E1XXX_INTR_MDI_XOVER_CHNG 0x0040 42f7917c00SJeff Kirsher #define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080 43f7917c00SJeff Kirsher #define MV88E1XXX_INTR_FALSE_CARRIER 0x0100 44f7917c00SJeff Kirsher #define MV88E1XXX_INTR_SYMBOL_ERROR 0x0200 45f7917c00SJeff Kirsher #define MV88E1XXX_INTR_LINK_CHNG 0x0400 46f7917c00SJeff Kirsher #define MV88E1XXX_INTR_AUTONEG_DONE 0x0800 47f7917c00SJeff Kirsher #define MV88E1XXX_INTR_PAGE_RECV 0x1000 48f7917c00SJeff Kirsher #define MV88E1XXX_INTR_DUPLEX_CHNG 0x2000 49f7917c00SJeff Kirsher #define MV88E1XXX_INTR_SPEED_CHNG 0x4000 50f7917c00SJeff Kirsher #define MV88E1XXX_INTR_AUTONEG_ERR 0x8000 51f7917c00SJeff Kirsher 52f7917c00SJeff Kirsher /* Marvell PHY specific registers. */ 53f7917c00SJeff Kirsher #define MV88E1XXX_SPECIFIC_CNTRL_REGISTER 16 54f7917c00SJeff Kirsher #define MV88E1XXX_SPECIFIC_STATUS_REGISTER 17 55f7917c00SJeff Kirsher #define MV88E1XXX_INTERRUPT_ENABLE_REGISTER 18 56f7917c00SJeff Kirsher #define MV88E1XXX_INTERRUPT_STATUS_REGISTER 19 57f7917c00SJeff Kirsher #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER 20 58f7917c00SJeff Kirsher #define MV88E1XXX_RECV_ERR_CNTR_REGISTER 21 59f7917c00SJeff Kirsher #define MV88E1XXX_RES_REGISTER 22 60f7917c00SJeff Kirsher #define MV88E1XXX_GLOBAL_STATUS_REGISTER 23 61f7917c00SJeff Kirsher #define MV88E1XXX_LED_CONTROL_REGISTER 24 62f7917c00SJeff Kirsher #define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER 25 63f7917c00SJeff Kirsher #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER 26 64f7917c00SJeff Kirsher #define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER 27 65f7917c00SJeff Kirsher #define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER 28 66f7917c00SJeff Kirsher #define MV88E1XXX_EXTENDED_ADDR_REGISTER 29 67f7917c00SJeff Kirsher #define MV88E1XXX_EXTENDED_REGISTER 30 68f7917c00SJeff Kirsher 69f7917c00SJeff Kirsher /* PHY specific control register fields */ 70f7917c00SJeff Kirsher #define S_PSCR_MDI_XOVER_MODE 5 71f7917c00SJeff Kirsher #define M_PSCR_MDI_XOVER_MODE 0x3 72f7917c00SJeff Kirsher #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE) 73f7917c00SJeff Kirsher #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE) 74f7917c00SJeff Kirsher 75f7917c00SJeff Kirsher /* Extended PHY specific control register fields */ 76f7917c00SJeff Kirsher #define S_DOWNSHIFT_ENABLE 8 77f7917c00SJeff Kirsher #define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE) 78f7917c00SJeff Kirsher 79f7917c00SJeff Kirsher #define S_DOWNSHIFT_CNT 9 80f7917c00SJeff Kirsher #define M_DOWNSHIFT_CNT 0x7 81f7917c00SJeff Kirsher #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT) 82f7917c00SJeff Kirsher #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT) 83f7917c00SJeff Kirsher 84f7917c00SJeff Kirsher /* PHY specific status register fields */ 85f7917c00SJeff Kirsher #define S_PSSR_JABBER 0 86f7917c00SJeff Kirsher #define V_PSSR_JABBER (1 << S_PSSR_JABBER) 87f7917c00SJeff Kirsher 88f7917c00SJeff Kirsher #define S_PSSR_POLARITY 1 89f7917c00SJeff Kirsher #define V_PSSR_POLARITY (1 << S_PSSR_POLARITY) 90f7917c00SJeff Kirsher 91f7917c00SJeff Kirsher #define S_PSSR_RX_PAUSE 2 92f7917c00SJeff Kirsher #define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE) 93f7917c00SJeff Kirsher 94f7917c00SJeff Kirsher #define S_PSSR_TX_PAUSE 3 95f7917c00SJeff Kirsher #define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE) 96f7917c00SJeff Kirsher 97f7917c00SJeff Kirsher #define S_PSSR_ENERGY_DETECT 4 98f7917c00SJeff Kirsher #define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT) 99f7917c00SJeff Kirsher 100f7917c00SJeff Kirsher #define S_PSSR_DOWNSHIFT_STATUS 5 101f7917c00SJeff Kirsher #define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS) 102f7917c00SJeff Kirsher 103f7917c00SJeff Kirsher #define S_PSSR_MDI 6 104f7917c00SJeff Kirsher #define V_PSSR_MDI (1 << S_PSSR_MDI) 105f7917c00SJeff Kirsher 106f7917c00SJeff Kirsher #define S_PSSR_CABLE_LEN 7 107f7917c00SJeff Kirsher #define M_PSSR_CABLE_LEN 0x7 108f7917c00SJeff Kirsher #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN) 109f7917c00SJeff Kirsher #define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN) 110f7917c00SJeff Kirsher 111f7917c00SJeff Kirsher #define S_PSSR_LINK 10 112f7917c00SJeff Kirsher #define V_PSSR_LINK (1 << S_PSSR_LINK) 113f7917c00SJeff Kirsher 114f7917c00SJeff Kirsher #define S_PSSR_STATUS_RESOLVED 11 115f7917c00SJeff Kirsher #define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED) 116f7917c00SJeff Kirsher 117f7917c00SJeff Kirsher #define S_PSSR_PAGE_RECEIVED 12 118f7917c00SJeff Kirsher #define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED) 119f7917c00SJeff Kirsher 120f7917c00SJeff Kirsher #define S_PSSR_DUPLEX 13 121f7917c00SJeff Kirsher #define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX) 122f7917c00SJeff Kirsher 123f7917c00SJeff Kirsher #define S_PSSR_SPEED 14 124f7917c00SJeff Kirsher #define M_PSSR_SPEED 0x3 125f7917c00SJeff Kirsher #define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED) 126f7917c00SJeff Kirsher #define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED) 127f7917c00SJeff Kirsher 128f7917c00SJeff Kirsher #endif 129