Searched +full:0 +full:xb8002000 (Results 1 – 9 of 9) sorted by relevance
36 reg = <0xb8002000 0x1000>;
38 * 0x00000000-0x7fffffff See i.MX25 SOC fr support39 * 0x80000000-0x87ffffff RAM + Alias EMULATED40 * 0x90000000-0x9fffffff RAM + Alias EMULATED41 * 0xa0000000-0xa7ffffff Flash IGNORED42 * 0xa8000000-0xafffffff Flash IGNORED43 * 0xb0000000-0xb1ffffff SRAM IGNORED44 * 0xb2000000-0xb3ffffff SRAM IGNORED45 * 0xb4000000-0xb5ffffff CS4 IGNORED46 * 0xb6000000-0xb8000fff Reserved IGNORED47 * 0xb8001000-0xb8001fff SDRAM CTRL reg IGNORED[all …]
16 #define AIC9410_DEV_REV_B0 0x819 #define REG_BASE_ADDR 0xB800000020 #define REG_BASE_ADDR_CSEQCIO 0xB800200021 #define REG_BASE_ADDR_EXSI 0xB804280023 #define MBAR0_SWA_SIZE 0x5825 #define MBAR0_SWC_SIZE 0x828 #define OCM_BASE_ADDR 0xA000000029 #define OCM_MAX_SIZE 0x2000037 #define PCI_CONF_MBAR1 0x6C38 #define PCI_CONF_MBAR0_SWA 0x70[all …]
16 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */17 #define IRAM_SIZE 0x00020000 /* 128 KB */19 #define LOW_LEVEL_SRAM_STACK 0x1001E00024 #define AIPS1_BASE_ADDR 0x43F0000026 #define MAX_BASE_ADDR 0x43F0400027 #define EVTMON_BASE_ADDR 0x43F0800028 #define CLKCTL_BASE_ADDR 0x43F0C00029 #define I2C1_BASE_ADDR 0x43F8000030 #define I2C3_BASE_ADDR 0x43F8400031 #define ATA_BASE_ADDR 0x43F8C000[all …]
24 #size-cells = <0>;26 cpu@0 {29 reg = <0>;37 #clock-cells = <0>;45 #clock-cells = <0>;57 reg = <0xb0000000 0x200>;62 reg = <0xb0000200 0x100>;71 reg = <0xb8000000 0x20>;76 pinctrl-0 = <&bsp_pins>;82 reg = <0xb8000100 0x20>;[all …]
35 #size-cells = <0>;37 cpu@0 {40 reg = <0>;48 reg = <0x68000000 0x100000>;60 reg = <0x1fffc000 0x4000>;63 ranges = <0 0x1fffc000 0x4000>;70 reg = <0x43f00000 0x100000>;75 reg = <0x43f80000 0x4000>;79 #size-cells = <0>;85 reg = <0x43f84000 0x4000>;[all …]
39 #size-cells = <0>;41 cpu@0 {44 reg = <0>;52 reg = <0x68000000 0x10000000>;64 reg = <0x30000000 0x1000>;73 reg = <0x43f00000 0x100000>;78 #size-cells = <0>;80 reg = <0x43f80000 0x4000>;89 #size-cells = <0>;91 reg = <0x43f84000 0x4000>;[all …]
27 u32 cgr0; /* Clock Gating Control 0 */33 u32 dcvr0; /* DPTC Comparator Value 0 */37 u32 ltr0; /* Load Tracking 0 */41 u32 ltbr0; /* Load Tracking Buffer 0 */43 u32 pcmr0; /* Power Management Control 0 */47 u32 lpimr0; /* Low Power Interrupt Mask 0 */53 u32 ctl0; /* control 0 */54 u32 cfg0; /* configuration 0 */104 u32 res1[0x1f1];106 u32 fuse_regs[0x20];[all …]
70 u32 res[0x1f1];72 u32 fuse_regs[0x20];73 u32 fuse_rsvd[0xe0];100 #define IOMUX_PADNUM_MASK 0x1ff107 PAD_CTL_NOLOOPBACK = 0x0 << 9,108 PAD_CTL_LOOPBACK = 0x1 << 9,109 PAD_CTL_PKE_NONE = 0x0 << 8,110 PAD_CTL_PKE_ENABLE = 0x1 << 8,111 PAD_CTL_PUE_KEEPER = 0x0 << 7,112 PAD_CTL_PUE_PUD = 0x1 << 7,[all …]